Functional Architecture Intel® Server Boards S3200SH/S3210SH TPS
18 Revision 1.8
Intel Order Number: E14960-009
Lane Device
Lane 0~7 Slot 6 (PCI Express* x16 with 8 Lanes layout)
3.2.1.2 MCH Memory Sub-System Overview
The MCH supports a 72-bit wide memory sub-system that can support a maximum of 8 GB of
DDR2 memory using 2 GB DIMMs. This configuration needs external registers for buffering the
memory address and control signals. The four chip selects are registered inside the MCH and
need no external registers for chip selects.
The memory interface runs at 667/800 MT/s. The memory interface supports a 72-bit wide
memory array. It uses seventeen address lines (BA [2:0] and MA [13:0]) and supports 512 MB,
1 GB, and 2 GB DRAM densities. The DDR DIMM interface supports single-bit error correction,
and multiple bit error detection.
3.2.1.3 DDR2 Configurations
The DDR2 interface supports up to 8 GB of main memory and supports single- and double-
density DIMMs. The DDR2 can be any industry-standard DDR2. The following table shows the
DDR2 DIMM technology supported.
Table 5. Supported DDR2 Modules
DDR2-667/800 Un-buffered
SDRAM Module Matrix
DIMM
Capacity
DIMM Organization
SDRAM
Density
SDRAM
Organization
# SDRAM
Devices/rows/Banks
# Address bits
rows/Banks/column
512 MB 64M x 72 256 Mbit 32M x 8 18 / 2 / 4 13 / 2 / 10
512 MB 64M x 72 512 Mbit 64M x 8 9 / 1 / 4 14 / 2 / 10
1 GB 128M x 72 512 Mbit 64M x 8 18 / 2 / 4 14 / 2 / 10
1 GB 128M x 72 1 Gbit 128M x 8 9 / 1 / 8 14 / 4 / 10
2 GB 256M x 72 2 GB 128M x 8 18 / 2 / 8 14 / 8 / 10
3.2.1.4 Memory Population Rules and Configurations
You must follow a few rules when populating memory. The server board supports two DDR2
DIMM slots for channel A and two DDR2 DIMM slots for channel B. They are placed in a row
and numbered from 0 to 3 with DIMM0 being closest to the MCH. The four slots are partitioned
with channel A representing the channel A DIMMs (DIMM0 and DIMM1) and channel B
representing the channel B DIMMs (DIMM2 and DIMM3).
Note the following memory population rules:
If dual-channel operation is needed, you must populate channel A and channel B
identically (for example, same capacity).
Use DDR2 667/800 MHz memory only.
The slowest DIMM in the system determines the speed used on all the channels.
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