Functional Architecture Intel® Server Boards S3200SH/S3210SH TPS
20 Revision 1.8
Intel Order Number: E14960-009
Baseboard Signals Device
PCIX REQ_N1/GNT_N1 PCI-X Slot 1 (64-bit/66-133 MHz) (LX board SKU only)
PCIX REQ_N0/GNT_N0 PCI-X Slot 2 (64-bit/66-133 MHz) ( LX board SKU only)
3.2.3 Intel
®
ICH9R: I/O Controller Hub 9R
3.2.3.1 Direct Media Interface (DMI)
DMI is the name given to the chip-to-chip connection between the Memory Controller Hub and
the Intel
®
ICH9. DMI is a x4 link that mostly adheres to the PCI Express* specification.
Deviations of the DMI from standard PCI Express* specifications are described in the Intel
®
ICH9 CSPEC.
3.2.3.2 Controller Link (M-Link)
Controller Link is the name given to the interconnect that connects the north bridge (MCH) to
the LAN Controller in the Intel
®
ICH9. The Management Engine (ME) resides in the MCH and
communicates with the ICH9 LAN Controller over this interface.
3.2.3.3 PCI Express* Interfaces
The ICH9R provides six PCI Express* root ports (GEN1) which are compliant with the PCI
Express* Base Specification, Revision 1.1. You can statically configure the PCI Express* root
ports 1-4 as four x 1 ports, or ganged together to form two x 2 ports, one x 2 with two x1 ports,
or one x4 port. Ports 5 and 6 can only be used as two x1 ports or one x2. The x4 configuration
supports lane reversal. Each Root Port fully supports 2.5 Gb/s bandwidth in each direction.
The root ports 1-4 are combined to form a single x4 link connecting to a PCI Express* x8
connector. Port 5 and 6 are used to support the dual GBe LAN channels.
3.2.3.4 Serial ATA II Interface
The Intel
®
ICH9 has an integrated SATA II host controller that supports independent DMA
operation on the six Ports and supports data transfer rates of up to 300 MB/Sec. The SATA II
controller provides two modes of operation – a legacy mode using I/O space and an Advanced
Host Controller Interface (AHCI) mode using memory space.
3.2.3.5 PCI Interface
The Intel
®
ICH9 PCI interface provides a 33 MHz, 3.3 V, Revision 2.3 implementation. Except
for PME#, all PCI signals are 5 V tolerant. The ICH9 integrates a PCI arbiter that supports up to
seven external PCI bus masters in addition to the internal ICH9 requests. This allows for
combinations of up to four PCI down devices and/or PCI slots.
The server board supports one NIC, the 82541PI Gigabit Ethernet controller, and two PCI slots.
3.2.3.6 Low Pin Count Interface (LPC)
The Low Pin Count interface on the Intel
®
ICH9 provides a low system cost design interface
solution for connecting the Super I/O for the legacy interfaces such as the parallel port, serial
port, floppy drive, and so on.
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