Functional Architecture Intel® Server Boards S3200SH/S3210SH TPS
38 Revision 1.8
Intel Order Number: E14960-009
3.6 PCI Express* to PCI-X Bridge 6702PXH (PXH-V) (LX Board SKU Only)
The Intel
®
6702PXH 64-bit PCI Hub is a peripheral chip that performs PCI bridging functions
between the PCI Express* interface and the PCI bus. The Intel
®
6702PXH 64-bit PCI Hub
contains a single PCI bus interface that can be configured to operate in PCI (33 or 66 MHz) or
PCI-X Mode 1 (66, 100, or 133 MHz).
The Intel
®
6702PXH 64-bit PCI Hub further supports the new PCI Standard Hot-Plug Controller
and Subsystem Specification, Revision 1.0. Each PCI interface contains an I/OxAPIC with 24
interrupts and a standard hot plug controller.
3.7 Clock Generator
A CK505 compliant Clock Synthesizer chip solution generates most of the required clocks on
the Intel
®
Server Board S3200SH. The CK505 synthesizes and distributes a multitude of clock
outputs at various frequencies, timings, and drive levels using a single parallel resonance
14.31818 MHz (50 ppm or less) crystal.
The CK505 clock generator supplies host clocks (at 200 MHz, 266 MHz, and 333 MHz),
100 MHz clocks, 48 MHz clocks, 33 MHz clocks, and 14 MHz clocks.
The CK505 has twelve SRC outputs targeted for PCI Express* applications at 100 MHz.
The CK505 is the main clock source for the entire system.
The clock generator supports the following:
o Differential host clock pairs for processor, MCH and XDP
o Differential 100 MHz to ICH9 (DMI and SATA), MCH, XDP, and PCI Express*
slots
o 33 MHz clocks for ICH9, SIO, SM712, Port 80/81h and PCI32 slots
o Single ended 48 MHz clock for the Intel
®
CH9 USB Controller
o Single ended 14.318 MHz clocks shared between the ICH9 and SIO
o Debug jumpers to manually select FSB/host clock frequency
SMBus interface for spread spectrum support
Option to retain register contents in PWRDWN# state
3.8 Super I/O
There is a Winbond* PC8374L super I/O located on the Intel
®
ICH9 LPC bus. This device uses
the following features on the server board:
LPC rev 1.1
Floppy Disk Controller with a Digital Data Separator
KB and Mouse Controller (KBC)
ACPI 2.0b Compliant
Sensor Path* Interface
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