Functional Architecture IntelĀ® Server Boards S3200SH/S3210SH TPS
32 Revision 1.8
Intel Order Number: E14960-009
3.4.3 PCI Error Handling
The PCI bus defines two error pins, PERR# and SERR#, for reporting PCI parity errors and
system errors, respectively. In the case of PERR#, the PCI bus master has the option to retry
the offending transaction or report it using SERR#. SERR# reports all other PCI-related errors. If
enabled by the BIOS, SERR# is routed to NMI.
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