Table 7: Protocols and Applications Supported by ACX Series Routers (continued)
ACX5096ACX5048ACX4000ACX2100ACX2000ACX1100ACX1000Protocol or Application
15.1X54–D2015.1X54–D2012.3x51-D1012.2R212.212.2R212.2Eight queues per port
15.1X54–D2015.1X54–D2012.3x51-D1012.2R212.212.2R212.2Priority queuing
15.1X54–D2015.1X54–D2012.3x51-D1012.2R212.212.2R212.2Rate control
15.1X54–D2015.1X54–D2012.3x51-D1012.2R212.212.2R212.2Scheduling with two
different priorities
15.1X54–D2015.1X54–D2012.3x51-D1012.2R212.212.2R212.2Low-latency queue (LLQ)
15.1X54–D2015.1X54–D2012.3x51-D1012.2R212.212.2R212.2Weighted random early
detection (WRED) drop
profile (DP)
15.1X54–D2015.1X54–D2012.3x51-D1012.2R212.212.2R212.2Classification—DSCP
15.1X54–D2015.1X54–D2012.3x51-D1012.2R212.212.2R212.2Classification—MPLS EXP
15.1X54–D2015.1X54–D2012.3x51-D1012.2R212.212.2R212.2Classification—IEEE 802.1p
15.1X54–D2015.1X54–D2012.3x51-D1012.2R212.212.2R212.2Rewrite—DSCP
15.1X54–D2015.1X54–D2012.3x51-D1012.2R212.212.2R212.2Rewrite MPLS EXP
15.1X54–D2015.1X54–D2012.3x51-D1012.2R212.212.2R212.2Rewrite 802.1p
15.1X54–D2015.1X54–D2012.3x51-D1012.2R212.212.2R212.2RewriteMPLSandDSCPto
different values
Timing
––12.3x51-D1012.2R212.212.2R212.2Timing-1588-v2,
1588-2008–backup clock
––12.3x51-D1012.2R212.212.2R212.2Synchronous Ethernet
––12.3x51-D1012.2R212.212.2R212.2Building-integrated timing
supply (BITS)
––12.3x51-D1012.2R212.212.2R212.2Clock synchronization
–––––––Redundant clock (multiple
1588 masters)
15.1X54-D2015.1X54-D20–––––Transparent clock
OAM, Troubleshooting, Manageability, Lawful Intercept
13Copyright © 2015, Juniper Networks, Inc.
Chapter 1: System Overview and Architecture
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