Direct digital synthesis (DDS) generators use a phase accumulation
technique to control waveform memory addressing. Instead of using a
counter to generate sequential memory addresses, an “adder” is used (see
the following page). On each clock cycle, the constant loaded into the phase
increment register (PIR) is added to the present result in the phase
accumulator. The most-significant bits of the phase accumulator output are
used to address waveform memory. By changing the PIR constant, the
number of clock cycles required to step through the entire waveform
memory changes, thus changing the output frequency.
The PIR determines how fast the phase value changes with time and
thereby controls the frequency being synthesized. More bits in the phase
accumulator result in finer frequency resolution. Since the PIR affects only
the rate of change of the phase value (and not the phase itself), changes in
waveform frequency are phase-continuous.
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