9 MULTIPLE CPU DEDICATED INSTRUCTIONS
9.2 Reading from the CPU Shared Memory of Another CPU
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• Reads the data of n3 words from the CPU shared memory address designated by n2 of the CPU module designated by n1,
and stores that data into the area starting from the device designated by (D).
*1 Usable as a user free area when auto refresh setting is not made.
When auto refresh setting is made, the auto refresh send range and later are usable as a user free area.
*2 With the following CPU modules, data cannot be read from the multiple CPU high speed transmission area.
Q00UCPU, Q01UCPU, Q02UCPU
• When 0 is specified in n3 as the number of data to be read, no processing is performed.
• The number of data to be read changes depending on the target CPU module.
• An instruction which has been executed will result in non-processing if it fails to access the target module because the
module is faulty or busy in processing.
• CPU shared memory address of the Basic model QCPU
• CPU shared memory address of the Universal model QCPU
*2
CPU module Number of read points
Basic model QCPU 1 to 512
Universal model QCPU 1 to 14336
Device memory
CPU shared memory of
the designated CPU (n1)
n3
Reads the
data of n3
words
n2
D
0(0H)
96(60H)
192(C0H)
511(1FFH)
Host CPU operation information area
CPU shared memory address
System area
Host CPU refresh area
*1
User free area
Read designation
permitted area
0(0H)
512(200H)
2048(800H)
4096(1000H)
10000(2710H)
24335(5F0FH)
Host CPU operation information area
CPU shared memory address
System area
Host CPU refresh area
*1
User free area
Read designation
permitted area
Unusable
Multiple CPU high speed
transmission area
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