Mitsubishi Electric MELSEC-Q/L - Page 861

9 MULTIPLE CPU DEDICATED INSTRUCTIONS
9.2 Reading from the CPU Shared Memory of Another CPU
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9
FROM(P)
■When High Performance model QCPU, Process CPU is used
*1 Specified with the upper three digits of the four hexadecimal digits representing the start I/O number.
The value of n1 is specified by the upper three digits of the four hexadecimal digits representing the start I/O number of the
slot where the CPU module has been mounted.
Processing details
• Reads the data of n3 words from the CPU shared memory address designated by n2 of the CPU module designated by n1,
and stores that data into the area starting from the device designated by (D).
• CPU shared memory address of the High Performance model QCPU and Process CPU
*2 Usable as a user free area when auto refresh setting is not made.
When auto refresh setting is made, the auto refresh send range and later are usable as a user free area.
n1: Start I/O number of the reading target CPU module
*1
(3E0H to 3E3H) (BIN 16 bits)
n2: Head address of data to be read (BIN 16 bits)
(D): Head number of the devices where the read data is stored (BIN 16 bits)
n3: Number of read data (BIN 16 bits)
Setting
data
Internal device R, ZR J\ U\G Zn Constant
K, H
Others
U
Bit Word Bit Word
n1   
n2   
(D)   
n3   
Slot number Head I/O number n1
CPU slot 3E00 3E0
Slot 0 3E10 3E1
Slot 1 3E20 3E2
Slot 2 3E30 3E3
Command
Command
n3
n3
n1
n1
n2
n2
D
D
FROM
FROMP
FROM
FROMP
Device memory
CPU shared memory of
the designated CPU (n1)
n3
Reads the
data of n3
words
n2
D
0(0H)
512(200H)
2048(800H)
4095(0FFFH)
CPU shared memory address
Host CPU operation information area
System area
Host CPU refresh area
*2
User free area
Read designation
permitted area