Mitsubishi MELSEC-Q QD77MS - Page 937

Appendix - 28
Appendices
The following shows the relation between the buffer memory addresses for mark
detection function and the various items.
(Note): Do not use the buffer memory address that not been described here for a
"Maker setting".
Buffer memory address
QD77MS2
QD77MS4
QD77MS16
Compatibility
of setting value
of QD77MS2/
QD77MS4 and
QD77MS16
Item
Memory
area
54000+20k
Pr.800 Mark detection signal setting
54001+20k
Pr.801 Mark detection signal compensation time
54002+20k
Pr.802 Mark detection data type
54003+20k
Pr.803 Mark detection data axis No.
54004+20k
54005+20k
Pr.804 Mark detection data buffer memory No.
54006+20k
54007+20k
Pr.805 Latch data range upper limit value
54008+20k
54009+20k
Pr.806 Latch data range lower limit value
54010+20k
Pr.807 Mark detection mode setting
Mark detection setting parameters
54640+10k
Cd.800 Number of mark detection clear request
54641+10k
Cd.801 Mark detection invalid flag
Mark
detection
control data
54960+80k
Md.800 Number of mark detection counter
54962+80k
54963+80k
1
54964+80k
54965+80k
2
54966+80k
54967+80k
3
to
to
55024+80k
55025+80k
Md.801 Mark detection data storage area
32
Mark detection monitor data
k: Mark detection setting No.-1
: Compatible : Partly compatible : Not compatible