Siemens SIPROTEC 4 7VE61 - Page 6

OR-gate operation of input values
Exclusive OR gate (antivalence): output is active, if only one of the
inputs is active
Coincidence gate: output is active, if both inputs are active or inactive
at the same time
Dynamic inputs (edge-triggered) above with positive, below with
negative edge
Formation of one analog output signal from a number of analog input
signals
Limit stage with setting address and parameter designator (name)
Timer (pickup delay T, example adjustable) with setting address and
parameter designator (name)
Timer (dropout delay T, example non-adjustable)
Dynamic triggered pulse timer T (monoflop)
Static memory (SR flipflop) with setting input (S), resetting input (R),
output (Q) and inverted output (Q), setting input dominant
Static memory (RS-flipflop) with setting input (S), resetting input (R),
output (Q) and inverted output (Q), resetting input dominant
Preface
6 SIPROTEC 4, 7VE61 and 7VE63, Manual
C53000-G1176-C163-3, Edition 10.2017