ST STM32G431 User Manual

Advanced-control timers (TIM1/TIM8/TIM20) RM0440
1102/2126 RM0440 Rev 4
Figure 283. Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6
1. Here, center-aligned mode 1 is used (for more details refer to Section 28.6: TIM1/TIM8/TIM20 registers).
Figure 284. Counter timing diagram, internal clock divided by 2
MSv62310V1
tim_psc_ck
tim_cnt_ck
Counter register
Update event (UEV)
Counter overflow
Update interrupt flag
(UIF)
00020304
05
06
01
CEN
02 03 0401 05 0304
Counter underflow
MSv62311V1
tim_psc_ck
CEN
tim_cnt_ck
Counter register
Update event (UEV)
Counter underflow
Update interrupt flag
(UIF)
0003
0002
0001
0000
0001
0002
0003

ST STM32G431 Specifications

General

Brand	ST
Model	STM32G431
Category	Microcontrollers
Language	English