Embedded Flash memory (FLASH) for category 3 devices RM0440
142/2126 RM0440 Rev 4
3.7.15 Flash Bank 2 WRP area A address register (FLASH_WRP2AR)
Address offset: 0x4C
Reset value: 0x00XX 00XX
Access: no wait state when no Flash memory operation is on going, word, half-word and
byte access
Bits 31:15 Reserved, must be kept cleared
Bits 14:0 PCROP2_END: PCROP area end offset
DBANK=1
PCROP2_END contains the last double-word of the PCROP area for bank2.
DBANK=0
PCROP2_END contains the last 2xdouble-word of the PCROP area for all the
memory.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. WRP2A_END[6:0]
rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. WRP2A_STRT[6:0]
rw rw rw rw rw rw rw
Bits 31:23 Reserved, must be kept cleared
Bits 22:16 WRP2A_END: WRP first area “A” end offset
DBANK=1
WRP2A_END contains the last page of the WRP first area for bank2.
DBANK=0
WRP2A_END contains the last page of the WRP third area for all memory.
Bits 15:7 Reserved, must be kept cleared
Bits 6:0 WRP2A_STRT: WRP first area “A” start offset
DBANK=1
WRP2A_STRT contains the first page of the WRP first area for bank2.
DBANK=0
WRP2A_STRT contains the first page of the WRP third area for all memory.
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