Flexible static memory controller (FSMC) RM0440
548/2126 RM0440 Rev 4
12 WREN 0x1
11 WAITCFG 0x0
10 Reserved 0x0
9 WAITPOL to be set according to memory
8 BURSTEN no effect on synchronous write
7 Reserved 0x1
6 FACCEN Set according to memory support
5-4 MWID As needed
3-2 MTYP 0x1
1 MUXEN As needed
0 MBKEN 0x1
Table 148. FMC_BTRx bitfields (Synchronous multiplexed write mode)
Bit number Bit name Value to set
31-30 DATAHLD Don’t care
29:28 ACCMOD 0x0
27-24 DATLAT Data latency
23-20 CLKDIV
0x0 to get CLK = HCLK
0x1 to get CLK = 2 × HCLK
19-16 BUSTURN Time between NEx high to NEx low (BUSTURN HCLK).
15-8 DATAST Don’t care
7-4 ADDHLD Don’t care
3-0 ADDSET Don’t care
Table 147. FMC_BCRx bitfields (Synchronous multiplexed write mode) (continued)
Bit number Bit name Value to set
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