Embedded Flash memory (FLASH) for category 3 devices RM0440
126/2126 RM0440 Rev 4
In RDP level 2, the debugger is disabled by hardware, but in other RDP levels, the debugger
can be disabled by software using the bit DBG_SWEN in the FLASH_ACR register.
Figure 11 gives an example of managing DBG_SWEN and SEC_PROT bits.
Figure 5. Example of disabling core debug access
3.5.6 Forcing boot from Flash memory
To increase the security and establish a chain of trust, the BOOT_LOCK option bit of the
FLASH_SEC1R/FLASH_SEC2R register allows forcing the system to boot from the Main
Flash memory regardless the other boot options. It is always possible to set the
BOOT_LOCK bit. However, it is possible to reset it only when:
• RDP is set to Level 0, or
• RDP is set to Level 1, while Level 0 is requested and a full mass-erase is performed.
3.6 FLASH interrupts
MSv42192V1
timeline
Debug
enabled
Debug
enabled
Debug
disabled
DBG_SWEN = 0 DBG_SWEN = 1 SEC_PROT = 1
Option
byte
loading
Execution of code
within securable memory
Execution of code
outside securable memory
Power up
SEC_PROT = 1
Securable memory secured
SEC_PROT = 0
Securable memory not secured
Software management
Table 16. Flash interrupt request
Interrupt event Event flag
Event flag/interrupt
clearing method
Interrupt enable control
bit
End of operation EOP
(1)
1. EOP is set only if EOPIE is set.
Write EOP=1 EOPIE
Operation error OPERR
(2)
2. OPERR is set only if ERRIE is set.
Write OPERR=1 ERRIE
Read error RDERR Write RDERR=1 RDERRIE
ECC correction ECCC Write ECCC=1 ECCCIE
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