ST STM32G431 User Manual

AES hardware accelerator (AES) RM0440
1504/2126 RM0440 Rev 4
ECB/CBC decryption sequence
The sequence of events to perform an AES ECB/CBC decryption is as follows (More detail
in Section 34.4.4).
1. Follow the steps described in Section 34.4.5: AES decryption round key preparation, in
order to prepare the decryption key in AES core.
2. Select the Mode 3 by setting to 10 the MODE[1:0] bitfield of the AES_CR register and
select ECB or CBC chaining mode by setting the CHMOD[2:0] bitfield of the AES_CR
register to 000 or 001, respectively. Data type can also be defined, using
DATATYPE[1:0] bitfield. KEYSIZE bitfield must be kept as-is.
3. Write the AES_IVRx registers with the initialization vector (required in CBC mode only).
4. Enable AES by setting the EN bit of the AES_CR register.
5. Write the AES_DINR register four times to input the cipher text (MSB first), as shown in
Figure 515.
6. Wait until the CCF flag is set in the AES_SR register.
7. Read the AES_DOUTR register four times to get the plain text (MSB first), as shown in
Figure 515. Then clear the CCF flag by setting the CCFC bit of the AES_CR register.
8. Repeat steps 5-6-7 to process all the blocks encrypted with the same key.
Figure 515. ECB/CBC decryption (Mode 3)
Suspend/resume operations in ECB/CBC modes
To suspend the processing of a message, proceed as follows:
1. If DMA is used, stop the AES DMA transfers to the IN FIFO by clearing the DMAINEN
bit of the AES_CR register.
2. If DMA is not used, read four times the AES_DOUTR register to save the last
processed block. If DMA is used, wait until the CCF flag is set in the AES_SR register
then stop the DMA transfers from the OUT FIFO by clearing the DMAOUTEN bit of the
AES_CR register.
3. If DMA is not used, poll the CCF flag of the AES_SR register until it becomes 1
(computation completed).
4. Clear the CCF flag by setting the CCFC bit of the AES_CR register.
5. Save initialization vector registers (only required in CBC mode as AES_IVRx registers
are altered during the data processing).
MS18938V3
WR
CT3
WR
CT2
WR
CT1
WR
CT0
Wait until flag CCF = 1
RD
PT3
RD
PT2
RD
PT1
RD
PT0
Input phase
4 write operations into
AES_DINR[31:0]
Computation phase
Output phase
4 read operations from
AES_DOUTR[31:0]
PT = plaintext = 4 words (PT3, … , PT0)
CT = ciphertext = 4 words (CT3, … , CT0)
MSB LSB MSB LSB

ST STM32G431 Specifications

General

Brand	ST
Model	STM32G431
Category	Microcontrollers
Language	English