RM0440 Rev 4 539/2126
RM0440 Flexible static memory controller (FSMC)
571
Figure 66. Muxed write access waveforms
The difference with mode D is the drive of the lower address byte(s) on the data bus.
Table 143. FMC_BCRx bitfields (Muxed mode)
Bit number Bit name Value to set
31:24 Reserved 0x000
23:22 NBLSET[1:0] As needed
20 CCLKEN As needed
19 CBURSTRW 0x0 (no effect in Asynchronous mode)
18:16 CPSIZE 0x0 (no effect in Asynchronous mode)
15 ASYNCWAIT Set to 1 if the memory supports this feature. Otherwise keep at 0.
14 EXTMOD 0x0
13 WAITEN 0x0 (no effect in Asynchronous mode)
12 WREN As needed
11 WAITCFG Don’t care
10 Reserved 0x0
9 WAITPOL Meaningful only if bit 15 is 1
8 BURSTEN 0x0
7 Reserved 0x1
6 FACCEN 0x1
MSv41686V1
A[25:16]
Memory transaction
NBL[x:0]
NEx
NOE
Data driven by controller
NWE
AD[15:0]
NBLSET
HCLK
cycles
ADDSET HCLK cycles DATAST HCLK cycles DATAHLD +1
HCLK cycles
ADDHLD
HCLK cycles
NADV
Lower address
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