General-purpose timers (TIM15/TIM16/TIM17) RM0440
1376/2126 RM0440 Rev 4
Re-directing tim_ocxref to tim_ocx or tim_ocxn
In output mode (forced, output compare or PWM), tim_ocxref can be re-directed to the
tim_ocx output or to tim_ocxn output by configuring the CCxE and CCxNE bits in the
TIMx_CCER register.
This allows to send a specific waveform (such as PWM or static active level) on one output
while the complementary remains at its inactive level. Other alternative possibilities are to
have both outputs at inactive level or both outputs active and complementary with dead-
time.
Note: When only tim_ocxn is enabled (CCxE=0, CCxNE=1), it is not complemented and becomes
active as soon as tim_ocxref is high. For example, if CCxNP=0 then tim_ocxn=tim_ocxref.
On the other hand, when both tim_ocx and tim_ocxn are enabled (CCxE=CCxNE=1)
tim_ocx becomes active when tim_ocxref is high whereas tim_ocxn is complemented and
becomes active when tim_ocxref is low.
30.4.15 Using the break function
The purpose of the break function is to protect power switches driven by PWM signals
generated with the timers. The break input is usually connected to fault outputs of power
stages and 3-phase inverters. When activated, the break circuitry shuts down the PWM
outputs and forces them to a predefined safe state.
The break channel gathers both system-level fault (clock failure, parity error,...) and
application fault (from input pins and built-in comparator), and can force the outputs to a
predefined level (either active or inactive) after a deadtime duration.
The output enable signal and output levels during break are depending on several control
bits:
• the MOE bit in TIMx_BDTR register allows to enable /disable the outputs by software
and is reset in case of break or break2 event.
• the OSSI bit in the TIMx_BDTR register defines whether the timer controls the output in
inactive state or releases the control to the GPIO controller (typically to have it in Hi-Z
mode)
• the OISx and OISxN bits in the TIMx_CR2 register which are setting the output shut-
down level, either active or inactive. The tim_ocx and tim_ocxn outputs cannot be set
both to active level at a given time, whatever the OISx and OISxN values. Refer to
Table 299: Output control bits for complementary tim_ocx and tim_ocxn channels with
break feature (TIM15) on page 1405 for more details.
When exiting from reset, the break circuit is disabled and the MOE bit is low. The break
function is enabled by setting the BKE bit in the TIMx_BDTR register. The break input
polarity can be selected by configuring the BKP bit in the same register. BKE and BKP can
be modified at the same time. When the BKE and BKP bits are written, a delay of 1 APB
clock cycle is applied before the writing is effective. Consequently, it is necessary to wait 1
APB clock period to correctly read back the bit after the write operation.
Because MOE falling edge can be asynchronous, a resynchronization circuit has been
inserted between the actual signal (acting on the outputs) and the synchronous control bit
(accessed in the TIMx_BDTR register). It results in some delays between the asynchronous
and the synchronous signals. In particular, if MOE is set to 1 whereas it was low, a delay
must be inserted (dummy instruction) before reading it correctly. This is because the write
acts on the asynchronous signal whereas the read reflects the synchronous signal.
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