Serial audio interface (SAI) RM0440
1806/2126 RM0440 Rev 4
SAI_xSR register) if less than half of the FIFO contains data (FLVL[2:0] bits in SAI_xSR
are less than 011b). This Interrupt (FREQ bit in SAI_xSR register) is cleared by hardware
when at least half of the FIFO contains data (FLVL[2:0] bits in SAI_xSR are higher or
equal to 011b).
• When the FIFO threshold bits in SAI_xCR2 register are configured as FIFO three quarter
(FTH[2:0] set to 011b), an interrupt is generated (FREQ bit is set by hardware to 1 in
SAI_xSR register) if less than three quarters of the FIFO contain data (FLVL[2:0] bits in
SAI_xSR are less than 0b100). This Interrupt (FREQ bit in SAI_xSR register) is cleared
by hardware when at least three quarters of the FIFO contain data (FLVL[2:0] bits in
SAI_xSR are higher or equal to 0b100).
• When the FIFO threshold bits in SAI_xCR2 register are configured as FIFO full (FTH[2:0]
set to 0b100), an interrupt is generated (FREQ bit is set by hardware to 1 in SAI_xSR
register) if the FIFO is not full (FLVL[2:0] bits in SAI_xSR is less than 101b). This Interrupt
(FREQ bit in SAI_xSR register) is cleared by hardware when the FIFO is full (FLVL[2:0]
bits in SAI_xSR is equal to 101b value).
Interrupt generation in reception mode
The interrupt generation depends on the FIFO configuration in reception mode:
• When the FIFO threshold bits in SAI_xCR2 register are configured as FIFO empty
(FTH[2:0] set to 0b000), an interrupt is generated (FREQ bit is set by hardware to 1 in
SAI_xSR register) if at least one data is available in SAI_xDR register(FLVL[2:0] bits in
SAI_xSR is higher or equal to 001b). This Interrupt (FREQ bit in SAI_xSR register) is
cleared by hardware when the FIFO becomes empty (FLVL[2:0] bits in SAI_xSR is equal
to 0b000) i.e no data are stored in FIFO.
• When the FIFO threshold bits in SAI_xCR2 register are configured as FIFO quarter fully
(FTH[2:0] set to 001b), an interrupt is generated (FREQ bit is set by hardware to 1 in
SAI_xSR register) if at least one quarter of the FIFO data locations are available
(FLVL[2:0] bits in SAI_xSR is higher or equal to 0b010). This Interrupt (FREQ bit in
SAI_xSR register) is cleared by hardware when less than a quarter of the FIFO data
locations become available (FLVL[2:0] bits in SAI_xSR is less than 0b010).
• When the FIFO threshold bits in SAI_xCR2 register are configured as FIFO half fully
(FTH[2:0] set to 0b010 value), an interrupt is generated (FREQ bit is set by hardware to
1 in SAI_xSR register) if at least half of the FIFO data locations are available (FLVL[2:0]
bits in SAI_xSR is higher or equal to 011b). This Interrupt (FREQ bit in SAI_xSR register)
is cleared by hardware when less than half of the FIFO data locations become available
(FLVL[2:0] bits in SAI_xSR is less than 011b).
• When the FIFO threshold bits in SAI_xCR2 register are configured as FIFO three quarter
full(FTH[2:0] set to 011b value), an interrupt is generated (FREQ bit is set by hardware to
1 in SAI_xSR register) if at least three quarters of the FIFO data locations are available
(FLVL[2:0] bits in SAI_xSR is higher or equal to 0b100). This Interrupt (FREQ bit in
SAI_xSR register) is cleared by hardware when the FIFO has less than three quarters of
the FIFO data locations avalable(FLVL[2:0] bits in SAI_xSR is less than 0b100).
• When the FIFO threshold bits in SAI_xCR2 register are configured as FIFO full(FTH[2:0]
set to 0b100), an interrupt is generated (FREQ bit is set by hardware to 1 in SAI_xSR
register) if the FIFO is full (FLVL[2:0] bits in SAI_xSR is equal to 101b). This Interrupt
(FREQ bit in SAI_xSR register) is cleared by hardware when the FIFO is not full
(FLVL[2:0] bits in SAI_xSR is less than 101b).
To Next Page
Loading...
Need help?
General
