FD controller area network (FDCAN) RM0440
1958/2126 RM0440 Rev 4
Debug mode behavior
in debug mode the set / reset on read feature is automatically disabled during the debugger
register access and enabled during normal MCU operation
Timeout counter
To signal timeout conditions for Rx FIFO 0, Rx FIFO 1, and the Tx Event FIFO the FDCAN
supplies a 16-bit Timeout Counter. It operates as downcounter and uses the same prescaler
controlled by TSCC[TCP] as the Timestamp Counter. The Timeout Counter is configured via
register TOCC. The actual counter value can be read from TOCV[TOC]. The Timeout
Counter can only be started while CCCR[INIT] = 0. It is stopped when CCCR[INIT] = 1, e.g.
when the FDCAN enters Bus_Off state.
The operation mode is selected by TOCC[TOS]. When operating in Continuous mode, the
counter starts when CCCR[INIT] is reset. A write to TOCV presets the counter to the value
configured by TOCC[TOP] and continues downcounting.
When the Timeout Counter is controlled by one of the FIFOs, an empty FIFO presets the
counter to the value configured by TOCC[TOP]. Downcounting is started when the first FIFO
element is stored. Writing to TOCV has no effect.
When the counter reaches 0, interrupt flag IR[TOO] is set. In Continuous mode, the counter
is immediately restarted at TOCC[TOP].
Note: The clock signal for the Timeout Counter is derived from the CAN core sample point signal.
Therefore the point in time where the Timeout Counter is decremented may vary due to the
synchronization / re-synchronization mechanism of the CAN core. If the baud rate switch
feature in FDCAN is used, the timeout counter is clocked differently in arbitration and data
fields.
44.3.3 Message RAM
The Message RAM has a width of 32 bits, and the FDCAN module is configured to allocate
up to 212 words in it. It is not necessary to configure each of the sections shown in
Figure 668.
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