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Universal serial bus full-speed device interface (USB) RM0440

2020/2126 RM0440 Rev 4

DBL_BUF setting, STAT bit pair is not affected by the transaction termination and its value

remains ‘11 (Valid). However, as the token packet of a new transaction is received, the

actual endpoint status will be masked as ‘10 (NAK) when a buffer conflict between the USB

peripheral and the application software is detected (this condition is identified by DTOG and

SW_BUF having the same value, see Table 409 on page 2019). The application software

responds to the CTR event notification by clearing the interrupt flag and starting any

required handling of the completed transaction. When the application packet buffer usage is

over, the software toggles the SW_BUF bit, writing ‘1 to it, to notify the USB peripheral about

the availability of that buffer. In this way, the number of NAKed transactions is limited only by

the application elaboration time of a transaction data: if the elaboration time is shorter than

the time required to complete a transaction on the USB bus, no re-transmissions due to flow

control will take place and the actual transfer rate will be limited only by the host PC.

The application software can always override the special flow control implemented for

double-buffered bulk endpoints, writing an explicit status different from ‘11 (Valid) into the

STAT bit pair of the related USB_EPnR register. In this case, the USB peripheral will always

use the programmed endpoint status, regardless of the buffer usage condition.

45.5.4 Isochronous transfers

The USB standard supports full speed peripherals requiring a fixed and accurate data

production/consume frequency, defining this kind of traffic as ‘Isochronous’. Typical

examples of this data are: audio samples, compressed video streams, and in general any

sort of sampled data having strict requirements for the accuracy of delivered frequency.

When an endpoint is defined to be ‘isochronous’ during the enumeration phase, the host

allocates in the frame the required bandwidth and delivers exactly one IN or OUT packet

each frame, depending on endpoint direction. To limit the bandwidth requirements, no re-

transmission of failed transactions is possible for Isochronous traffic; this leads to the fact

that an isochronous transaction does not have a handshake phase and no ACK packet is

expected or sent after the data packet. For the same reason, Isochronous transfers do not

support data toggle sequencing and always use DATA0 PID to start any data packet.

The Isochronous behavior for an endpoint is selected by setting the EP_TYPE bits at ‘10 in

its USB_EPnR register; since there is no handshake phase the only legal values for the

STAT_RX/STAT_TX bit pairs are ‘00 (Disabled) and ‘11 (Valid), any other value will produce

results not compliant to USB standard. Isochronous endpoints implement double-buffering

to ease application software development, using both ‘transmission’ and ‘reception’ packet

memory areas to manage buffer swapping on each successful transaction in order to have

always a complete buffer to be used by the application, while the USB peripheral fills the

other.

The memory buffer which is currently used by the USB peripheral is defined by the DTOG

bit related to the endpoint direction (DTOG_RX for ‘reception’ isochronous endpoints,

DTOG_TX for ‘transmission’ isochronous endpoints, both in the related USB_EPnR

ST STM32G431 User Manual

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