RM0440 Rev 4 295/2126
RM0440 Reset and clock control (RCC)
338
Bit 16 PLLPEN: Main PLL PLL “P” clock output enable
Set and reset by software to enable the PLL “P” clock output of the PLL.
In order to save power, when the PLL “P” clock output of the PLL is not used, the value of
PLLPEN should be 0.
0: PLL “P” clock output disable
1: PLL “P” clock output enable
Bit 15 Reserved, must be kept at reset value.
Bits 14:8 PLLN[6:0]: Main PLL multiplication factor for VCO
Set and cleared by software to control the multiplication factor of the VCO. These bits can be
written only when the PLL is disabled.
VCO output frequency = VCO input frequency x PLLN with 8 =< PLLN =< 127
0000000: PLLN = 0 wrong configuration
0000001: PLLN = 1 wrong configuration
...
0000111: PLLN = 7 wrong configuration
0001000: PLLN = 8
0001001: PLLN = 9
...
1111111: PLLN = 127
Caution: The software has to set correctly these bits to assure that the VCO
output frequency is within the range defined in the device datasheet.
Bits 7:4 PLLM[3:0]: Division factor for the main PLL input clock
Set and cleared by software to divide the PLL input clock before the VCO. These bits can be
written only when all PLLs are disabled.
VCO input frequency = PLL input clock frequency / PLLM with 1 <= PLLM <= 16
0000: PLLM = 1
0001: PLLM = 2
0010: PLLM = 3
0011: PLLM = 4
0100: PLLM = 5
0101: PLLM = 6
0110: PLLM = 7
0111: PLLM = 8
1000: PLLSYSM = 9
...
1111: PLLSYSM= 16
Caution: The software has to set these bits correctly to ensure that the VCO input
frequency is within the range defined in the device datasheet.
Bits 3:2 Reserved, must be kept at reset value.
Bits 1:0 PLLSRC[1:0]: Main PLL entry clock source
Set and cleared by software to select PLL clock source. These bits can be written only when
PLL is disabled.
In order to save power, when no PLL is used, the value of PLLSRC should be 00.
00: No clock sent to PLL
01: No clock sent to PLL
10: HSI16 clock selected as PLL clock entry
11: HSE clock selected as PLL clock entry
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