Analog-to-digital converters (ADC) RM0440
614/2126 RM0440 Rev 4
21.4.7 Single-ended and differential input channels
Channels can be configured to be either single-ended input or differential input by
programming DIFSEL[i] bits in the ADC_DIFSEL register. This configuration must be written
while the ADC is disabled (ADEN=0). Note that the DIFSEL[i] bits corresponding to single-
ended channels are always programmed at 0.
In single-ended input mode, the analog voltage to be converted for channel “i” is the
difference between the external voltage V
INP[i]
(positive input) and V
REF−
(negative input).
In differential input mode, the analog voltage to be converted for channel “i” is the difference
between the external voltage V
INP[i]
(positive input) and V
INN[i]
(negative input).
The input voltage in differential mode ranges from V
REF-
to V
REF+
, which makes a full scale
range of 2xV
REF+
. When V
INP[i]
equals V
REF-
, V
INN[i]
equals V
REF+
and the maximum
negative input differential voltage (V
REF-
) corresponds to 0x000 ADC output. When V
INP[i]
equals V
REF+
, V
INN[i]
equals V
REF-
and the maximum positive input differential voltage
(V
REF+
) corresponds to 0xFFF ADC output. When V
INP[i]
and V
INN[i]
are connected together,
the zero input differential voltage corresponds to 0x800 ADC output.
The ADC sensitivity in differential mode is twice smaller than in single-ended mode.
When ADC is configured as differential mode, both inputs should be biased at (V
REF+
) / 2
voltage. Refer to the device datasheet for the allowed common mode input voltage V
CMIN
.
The input signals are supposed to be differential (common mode voltage should be fixed).
Internal channels (such as V
TS
and V
REFINT
) are used in single-ended mode only.
For a complete description of how the input channels are connected for each ADC, refer to
Section 21.4.4: ADC1/2/3/4/5 connectivity.
Caution: When configuring the channel “i” in differential input mode, its negative input voltage V
INN[i]
is connected to another channel. As a consequence, this channel is no longer usable in
single-ended mode or in differential mode and must never be configured to be converted.
Some channels are shared between ADC1/ADC2/ADC3/ADC4/ADC5: this can make the
channel on the other ADC unusable. The only exception is when ADC master and the slave
operate in interleaved mode.
21.4.8 Calibration (ADCAL, ADCALDIF, ADC_CALFACT)
Each ADC provides an automatic calibration procedure which drives all the calibration
sequence including the power-on/off sequence of the ADC. During the procedure, the ADC
calculates a calibration factor which is 7-bit wide and which is applied internally to the ADC
until the next ADC power-off. During the calibration procedure, the application must not use
the ADC and must wait until calibration is complete.
Calibration is preliminary to any ADC operation. It removes the offset error which may vary
from chip to chip due to process or bandgap variation.
The calibration factor to be applied for single-ended input conversions is different from the
factor to be applied for differential input conversions:
• Write ADCALDIF=0 before launching a calibration which will be applied for single-
ended input conversions.
• Write ADCALDIF=1 before launching a calibration which will be applied for differential
input conversions.
To Next Page
Loading...
Need help?
General
