ST STM32H7 Series User Manual

PM0214 Rev 9 145/262
PM0214 The STM32 Cortex-M4 instruction set
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3.9.7 IT
If-Then condition instruction.
Syntax
IT{x{y{z}}} cond
Where:
• ‘x’ specifies the condition switch for the second instruction in the IT block.
• ‘y’ specifies the condition switch for the third instruction in the IT block.
• ‘z’ specifies the condition switch for the fourth instruction in the IT block.
• ‘cond’ specifies the condition for the first instruction in the IT block.
The condition switch for the second, third and fourth instruction in the IT block can be either:
T: Then. Applies the condition cond to the instruction.
E: Else. Applies the inverse condition of cond to the instruction.
a) It is possible to use AL (the always condition) for cond in an IT instruction. If this is
done, all of the instructions in the IT block must be unconditional, and each of x, y,
and z must be T or omitted but not E.
Operation
The IT instruction makes up to four following instructions conditional. The conditions can be
all the same, or some of them can be the logical inverse of the others. The conditional
instructions following the IT instruction form the IT block.
The instructions in the IT block, including any branches, must specify the condition in the
{cond} part of their syntax.
Your assembler might be able to generate the required IT instructions for conditional
instructions automatically, so that you do not need to write them yourself. See your
assembler documentation for details.
A BKPT instruction in an IT block is always executed, even if its condition fails.
Exceptions can be taken between an IT instruction and the corresponding IT block, or within
an IT block. Such an exception results in entry to the appropriate exception handler, with
suitable return information in LR and stacked PSR.
Instructions designed for use for exception returns can be used as normal to return from the
exception, and execution of the IT block resumes correctly. This is the only way that a PC-
modifying instruction is permitted to branch to an instruction in an IT block.
Restrictions
The following instructions are not permitted in an IT block:
• IT
• CBZ and CBNZ
• CPSID and CPSIE.

ST STM32H7 Series Specifications

General

Brand	ST
Model	STM32H7 Series
Category	Computer Hardware
Language	English

Summary

About this document

Typographical Conventions

Defines formatting used in the document for clarity.

List of Abbreviations for Registers

Provides a list of abbreviations used in register descriptions for quick reference.

STM32 Cortex-M4 Processor Overview

Introduces the STM32 Cortex-M4 processor's architecture and key features.

The Cortex-M4 Processor

Programmer's Model

Describes registers, modes, and privilege levels for software execution.

Memory Model

Details the processor's memory map, access behavior, and bit-banding features.

Exception Model

Explains exception states, types, priorities, and handling mechanisms.

Fault Handling

Covers fault types, escalation, status registers, and lockup conditions.

Power Management

Describes mechanisms for entering and exiting low-power sleep modes.

The STM32 Cortex-M4 Instruction Set

Instruction Set Summary

Lists supported Cortex-M4 instructions and their organization.

Memory Access Instructions

Details instructions for loading and storing data from/to memory.

General Data Processing Instructions

Explains instructions for arithmetic, logical, and data manipulation.

Multiply and Divide Instructions

Describes instructions for multiplication and division operations.

Floating-Point Instructions

Details instructions for FPU operations, including VFPv4-SP extension.

Miscellaneous Instructions

Covers instructions like breakpoints, barriers, and supervisor calls.

Core Peripherals

About the STM32 Cortex-M4 Core Peripherals

Introduces the core peripherals accessible via the Private Peripheral Bus (PPB).

Memory Protection Unit (MPU)

Explains the MPU for memory region definition and access control.

Nested Vectored Interrupt Controller (NVIC)

Describes the NVIC for managing interrupts and exceptions with priority levels.

System Control Block (SCB)

Details registers for system control, configuration, and exception reporting.

SysTick Timer (STK)

Explains the 24-bit SysTick timer for system timing and RTOS ticks.

Floating Point Unit (FPU)

Describes the FPU for single-precision floating-point operations.

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