Sun Microelectronics
136
UltraSPARC User’s Manual
7.16.10 ReadToShare Dirty Victimized Block
Condition: Load miss by another processor (P2) on a dirty line for which Proces-
sor 1’s Writeback transaction has not yet completed.
The following transaction sequence is the same as is Section 7.16.8, “Victim Write-
back,” except that another processor (P2) makes a ReadToShare request for the
victimized block in P1 before SC has acknowledged P1’s Writeback transaction.
Start read from memory
S_RBU reply to P1
P1 reads the data
updates Etag2{I → E}
Final state:
No change
Final state:
No change
Table 7-34 Copyback Dirty Victimized Block
Processor 1 System Processor 2 Processor 3
Initial victim state:
Etag1{M}
Initial missed state:
Etag2{I}
P1 copies the victimized block into the
writeback buffer}
P_RDS_REQ to System
(DVP bit set)
Initial state:
Etag1{I}
Initial state:
Etag2{I}
Initial state:
Etag2{I}
S_RBU reply to P1
P1 reads the data,
updates Etag2{I → E}
P_RDS_REQ to System
for the victim block in P1
S_CPB_REQ to P1
P1 makes another copy of the victim
block into the copyback buffer
P_SACKD or P_SACK reply to System
S_CRAB reply to P1
S_RBS reply to P2
P2 reads data and
updates Etag1{I → S}
P_WRB_REQ to System
S_WAB reply to P1
P1 clears writeback buffer tag Final State: No change Final state: Etag1{S} Final state: No change
Table 7-33 Victim Writeback: Writeback Serviced Before Read Miss
Processor 1 System Processor 2 Processor 3
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