Tektronix 1730 Series - Figure 4-6: Relative Line Select Elements for the 2-Line Display; Figure 4-4: Simplified Representation of the AFC Phase-Lock Loop. 4-12.; Figure 4-5: Elements for Line Select Timing.

1730–Series Theory of Operation
4–15
COMP SYNC
H SYNC
LIN SEL EN
LISEL
LIN STRB
PIXSTRB
H LIN SEL EN
2H SWEEP
(LOW)
(HIGH)
DISPLAYED LINES
Figure 4-6: Relative line select elements for the 2-line display.
In addition, U535 decodes instructions for selecting either the applied sync (CAL
high) or the Calibrator (CAL low) for the source of line rate sync (H TRIG).
Displaying the appropriate lines in the LINE SELECT mode is achieved by
blanking the CRT beam the rest of the time. The LIN SEL signal from the
Microprocessor is used by U735 to generate LINSTRB
, which is the blanking
signal, and PIXSTRB
, which is the strobe signal for the rear-panel Picture
Monitor Output. See Figure 4-5 for timing details.
Figure 4-6 and Figure 4-7 are timing diagrams that show the signal relationships
for 2 Line and 1 Line sweep rates in the LINE SELECT mode.
Horizontal and vertical triggering signals enable integrator sweep generators, by
dictating when retrace occurs. The output of the selected sweep generator drives
a Magnifier Amplifier, which provides sweep magnification, RGB staircase
input, and positioning control. The output of the Magnifier Amplifier drives the
Output Amplifier to match gain and impedance for the CRT deflection plates.
When 1 or 2-line Line Select is displayed readout is switched into the Output
Amplifier, for CRT display, on a time sharing basis with the sweep information.