ADC Timing – Simultaneous Sampling
7 Clocks
Sample
13 Clocks
Convert “A” Channel
2 Clocks
Write
2 Clocks
Latch
Generate Early
Interrupt “A” Channel
Generate Late
Interrupt “A” Channel
Start Sampling Next Channel
&
Generate Early
Interrupt “B” Channel
6 Clocks 7 Clocks
Convert “B” Channel
2 Clocks
Write
Generate Late
Interrupt “B” Channel
Max Continuous Sampling:
45 MHz
26 cycles / 2 sample
= 3.46 MSPS
Note: Sampling window of 7 cycles is minimum and it can be larger
Analog-to-Digital Converter Registers
AdcRegs.register (lab file: Adc.c)
ADCCTL1 Control 1 Register
ADCCTL2 Control 2 Register
ADCSOCxCTL SOC0 to SOC15 Control Registers
ADCINTSOCSELx Interrupt SOC Selection 1 and 2 Registers
ADCSAMPLEMODE Sampling Mode Register
ADCSOCFLG1 SOC Flag 1 Register
ADCSOCFRC1 SOC Force 1 Register
ADCSOCOVF1 SOC Overflow 1 Register
ADCSOCOVFCLR1 SOC Overflow Clear 1 Register
INTSELxNy Interrupt x and y Selection Registers
ADCINTFLG Interrupt Flag Register
ADCINTFLGCLR Interrupt Flag Clear Register
ADCINTOVF Interrupt Overflow Register
ADCINTOVFCLR Interrupt Overflow Clear Register
SOCPRICTL SOC Priority Control Register
ADCREFTRIM Reference Trim Register
ADCOFFTRIM Offset Trim Register
ADCREV Revision Register – reserved
ADCRESULTx ADC Result 0 to 15 Registers
Register Description
Note: ADCRESULTx header file coding is AdcResult.ADCRESULTx (not in AdcRegs)