Control Law Accelerator (CLA)
10 - 4 C2000 Microcontroller Workshop - Control Law Accelerator
CLA Memory and Register Access
CLA Memory and Register Access
Contains CLA program code
Mapped to the CPU at reset
Initialized by the CPU
CLA Program Memory
Used to pass data between
the CPU and CLA
Always mapped to both
the CPU and CLA
Message RAMs
Contains variables and coefficients
used by the CLA program code
Mapped to the CPU at reset
Initialized by CPU
CLA Data Memory
L3 DPSARAM L1 DPSARAM L2 DPSARAM PF0 PF0 & PF1
MSG RAMs
CPU to CLA
CLA to CPU
Program
RAM
Data
RAM0
Data
RAM1
Data
RAM2
L0 DPSARAM
Periph. Regs
ADC Results
ePWM
HRPWM
Comparator
eCAP
eQEP
ADC Results Regs
ePWM (all regs)
HRPWM (all regs)
Peripheral Reg Access
Comparator (all regs)
eCAP (all regs)
eQEP (all regs)
(4Kw) (1Kw) (1Kw) (2Kw)
(128w/128w)
CLA Tasks
CLA Tasks
A Task is similar to an interrupt service routine
CLA supports 8 Tasks (Task1-8)
A task is started by a peripheral interrupt trigger
Triggers are enabled in the MPISRCSEL1 register
When a trigger occurs the CLA begins execution at
the associated task vector entry (MVECT1-8)
Once a task begins it runs to completion (no nesting)
MPERINT1-8
CLA_INT1-8
LVF, LUF
PIE
C28x
CPU
INT11
INT12
CLA
Control & Execution
Registers
Task Triggers
(Peripheral Interrupts)
ADCINT1 to
ADCINT8
EPWM1_INT to
EPWM8_INT
ECAP1_INT to
ECAP3_INT
EQEP1_INT to
EQEP2_INT
CPU Timer 0