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Texas Instruments C2000

Texas Instruments C2000
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Analog-to-Digital Converter
6 - 8 C2000 Microcontroller Workshop - Analog-to-Digital Converter
ADC Clock and Timing
ADC Clocking Flow
Internal
OSC1
(10 MHz)
ADCCLK (45 MHz)
To ADC
pipeline
sampling
window
ACQ_PS
bits
ADCSOCxCTL
0110b
SYSCLKOUT
(90 MHz)
PLLSTS
DIVSEL
bits
10b (/2)
To CPU
sampling window = (ACQ_PS + 1)*(1/ADCCLK)
PCLKCR0.ADCENCLK = 1
PLLCR
DIV
bits
10010b (x18)
ADCCTL2
CLKDIV
bits
001b (/2)
ADC Timing Sequential Sampling
7 Clocks
Sample
6 Clocks 7 Clocks
Convert
2 Clocks
Write
2 Clocks
Latch
Generate Early
Interrupt
Generate Late
Interrupt
Start Sampling Next Channel
Max Continuous Sampling:
45 MHz
13 cycles / 1 sample
= 3.46 MSPS
Note: Sampling window of 7 cycles is minimum and it can be larger

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