Write-Read Protection
DevEmuRegs.DEVICECNF.bit.ENPROT
CPU pipeline protects W-R order for the same address
Write-Read protection mechanism protects W-R order for
different addresses
Peripheral Frame 0 and Peripheral Frame 1 zones protected
Write-read protection mode bit ENPROT located in the DEVICECNF
register is enabled by default
Suppose you need to write to a peripheral register and
then read a different register for the same peripheral
(e.g., write to control, read from status register)?
Peripheral Frame Registers
PF0
eCAN
COMP
ePWM
eCAP
eQEP
LIN
GPIO
PF1
System Control
SPI
SCI
Watchdog
XINT
ADC
I2C
Protected address:
0x4000 - 0x7FFF
EALLOW Protection
(1 of 2)
EALLOW stands for Emulation Allow
Code access to protected registers allowed
only when EALLOW = 1 in the ST1 register
The emulator can always access protected
registers
EALLOW bit controlled by assembly level
instructions
‘EALLOW’ sets the bit (register access enabled)
‘EDIS’ clears the bit (register access disabled)
EALLOW bit cleared upon ISR entry, restored
upon exit
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