SCI Data Timing
Start bit valid if 4 consecutive SCICLK periods of
zero bits after falling edge
Majority vote taken on 4
th
, 5
th
, and 6
th
SCICLK cycles
Start Bit
LSB of Data
Majority
Vote
Falling Edge Detected
SCIRXD
SCICLK
(Internal)
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2
Note: 8 SCICLK periods per data bit
Multiprocessor Wake-Up Modes
Allows numerous processors to be hooked
up to the bus, but transmission occurs
between only two of them
Idle-line or Address-bit modes
Sequence of Operation
1. Potential receivers set SLEEP = 1, which disables RXINT except
when an address frame is received
2. All transmissions begin with an address frame
3. Incoming address frame temporarily wakes up all SCIs on bus
4. CPUs compare incoming SCI address to their SCI address
5. Process following data frames only if address matches