DMA Throughput
4 cycles/word
(5 for McBSP reads)
1 cycle delay to start each burst
1 cycle delay returning from CH1
high priority interrupt
32-bit transfer doubles throughput
(except McBSP, which supports 16-bit transfers only)
Example: 128 16-bit words from ADC to RAM
8 bursts * [(4 cycles/word * 16 words/burst) + 1] = 520 cycles
Example: 64 32-bit words from ADC to RAM
8 bursts * [(4 cycles/word * 8 words/burst) + 1] = 264 cycles