What is the TMS320C2000™?
C2000 Microcontroller Workshop - Architecture Overview 1 - 3
What is the TMS320C2000™?
The TMS320C2000™ is a 32-bit fixed point microcontroller that specializes in high performance
control applications such as, robotics, industrial automation, mass storage devices, lighting,
optical networking, power supplies, and other control applications needing a single processor to
solve a high performance application.
TMS320F2806x Block Diagram
Sectored
Flash
Program Bus
Data Bus
RAM
Boot
ROM
3
32-bit
Timers
PIE
Interrupt
Manager
eQEP
Watchdog
I2C
SCI
SPI
GPIO
eCAP
CLA
CAN 2.0B
12-bit ADC
CLA Bus
32x32 bit
Multiplier
CPU
Register Bus
R-M-W
Atomic
ALU
FPU
VCU
DMA
6 Ch.
DMA Bus
McBSP
ePWM
USB 2.0
This block diagram represents an overview of all device features and is not specific to any one
device. The F28069 device is designed around a multibus architecture, also known as a modified
Harvard architecture. This can be seen in the block diagram by the separate program bus and data
bus, along with the link between the two buses. This type of architecture greatly enhances the
performance of the device.
In the upper left area of the block diagram, you will find the memory section, which consists of
the boot ROM, sectored flash, and RAM. Also, you will notice that the six-channel DMA has its
own set of buses.
In the lower left area of the block diagram, you will find the execution section, which consists of
a 32-bit by 32-bit hardware multiplier, a read-modify-write atomic ALU, a floating-point unit,
and a Viterbi complex math CRC unit. The control law accelerator coprocessor is an independent
and separate unit that has its own set of buses.
The peripherals are grouped on the right side of the block diagram. The upper set is the control
peripherals, which consists of the ePWM, eCAP, eQEP, and ADC. The lower set is the
communication peripherals and consists of the multichannel buffered serial port, I2C, SCI, SPI,
CAN, and USB.
The PIE block, or Peripheral Interrupt Expansion block, manages the interrupts from the
peripherals. In the bottom right corner is the general-purpose I/O. Also, the CPU has a watchdog
module and three 32-bit general-purpose timers available.
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