Viterbi Instructions
Viterbi Operation Example Instruction Cycles
Clear Viterbi Transition
Registers (VT0, VT1)
VTCLEAR
1
Double Add andSubtract
(low or high)
VITDLADDSUB VR4,VR3,VR2,VRa
VITDHADDSUB VR4,VR3,VR2,VRa
1
1
Double Subtract and Add
(low or high)
VITDLSUBADD VR4,VR3,VR2,VRa
VITDHSUBADD VR4,VR3,VR2,VRa
1
1
Branch Metrics Calculation
Code Rate = 1/2 or 1/3
VBITM2 VR0
VBITM3 VR0, VR1, VR2
1
2p
Viterbi Select
(low or high)
VITLSEL VRa, VRb, VR4, VR3
VITHSEL VRa, VRb, VR4, VR3
1
1
Trace Back
VTRACE mem32, VR0, VT0, VT1
VTRACE VR1, VR0, VT0, VT1
1
1
Double Add and Subtract or
Subtract and Add
with Parallel Store
VITDLADDSUB VR4,VR3,VR2,VRa
||VMOV32 mem32,VRb
1/1
Branch Matric (CR=1/2 or 1/3)
with Parallel Load
VBITM3 VR0, VR1, VR2
||VMOV32 VR2, mem32
2p/1**
Viterbi Select
with Parallel Load
VITLSEL VRa,VRb,VR4,VR3
||VMOV32 VR2, mem32
1/1
** VBITM2 || VMOV32 (For CR = 1/2) cycles are 1/1
Complex Math Unit
Supports 16-bit complex number calculations
Arithmetic, complex filters, and complex FFT
Complex addition and subtraction (1-cycle)
Complex multiplication
16-bit x 16-bit = 32-bit real and imaginary parts (2
pipelined cycles)
2-cycle Complex multiply and accumulate (MAC)
Repeat (RPT ||) complex MAC operation
Complex number: a + bj
a = real part
b = imaginary part j
2
= -1
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