Code Execution Performance
Assume 90 MHz SYSCLKOUT, 16-bit instructions
(80% of instructions are 16 bits wide – Rest are 32 bits)
Internal RAM: 90 MIPS
Fetch up to 32-bits every cycle 1 instruction/cycle * 90 MHz = 90 MIPS
Flash (w/ pipelining): 90 MIPS
RANDWAIT = 3
Fetch 64 bits every 3 cycles, but it will take 4 cycles to execute them
4 instructions/4 cycles * 90 MHz = 90 MIPS
RPT will increase this; PC discontinuity will degrade this
Benchmarking in control applications has shown actual performance of about 81 MIPS
Data Access Performance
Assume 90 MHz SYSCLKOUT
Internal RAM has best data performance – put time critical data here
Flash performance usually sufficient for most constants and tables
Note that the flash instruction fetch pipeline will also stall during a
flash data access
Memory 16-bit access 32-bit access Notes
(words/cycle) (words/cycle)
Internal RAM 1 1
Flash 0.33 0.33
RANDWAIT = 2
Flash is read only!
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