Lab 5: System Initialization
5 - 24 C2000 Microcontroller Workshop - System Initialization
follows. While the code was running, the watchdog timed out and reset the processor.
The reset vector was then fetched and the ROM bootloader began execution. Since the
device is in emulation boot mode (i.e. the emulator is connected) the bootloader read the
EMU_KEY and EMU_BMODE values from the PIE RAM. These values were
previously set for boot to M0 SARAM boot mode by CCS. Since these values did not
change and are not affected by reset, the bootloader transferred execution to the
beginning of our code at address 0x000000 in the M0SARAM, and execution continued
until the breakpoint was hit in main( ).
Setup PIE Vector for Watchdog Interrupt
The first part of this lab exercise used the watchdog to generate a CPU reset. This was tested
using a breakpoint set at the beginning of main(). Next, we are going to use the watchdog
to generate an interrupt. This part will demonstrate the interrupt concepts learned in the
previous module.
18. In the “CCS Edit Perspective” view add (copy) the following files to the project from
C:\C28x\Labs\Lab5\Files:
DefaultIsr_5.c
PieCtrl.c
PieVect.c
Check your files list to make sure the files are there.
19. In Main_5.c, add code to call the InitPieCtrl() function. There are no passed
parameters or return values, so the call code is simply:
InitPieCtrl();
20. Using the “PIE Interrupt Assignment Table” shown in the previous module find the
location for the watchdog interrupt, “WAKEINT”. This will be used in the next step.
PIE group #: # within group:
21. Modify main() to do the following:
- Enable global interrupts (INTM bit)
Then modify InitWatchdog() to do the following:
- Enable the “WAKEINT” interrupt in the PIE (Hint: use the
PieCtrlRegs structure)
- Enable the appropriate core interrupt in the IER register
22. In Watchdog.c modify the system control and status register (SCSR) to cause the
watchdog to generate a WAKEINT rather than a reset. Save all changes to the files.
23. Open and inspect DefaultIsr_5.c. This file contains interrupt service routines. The
ISR for WAKEINT has been trapped by an emulation breakpoint contained in an inline
assembly statement using “ESTOP0”. This gives the same results as placing a breakpoint
in the ISR. We will run the lab exercise as before, except this time the watchdog will
generate an interrupt. If the registers have been configured properly, the code will be
trapped in the ISR.
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