Service Guide 12-15
8719ET/20ET/22ET Theory of Operation
8719ES/20ES/22ES Source Group Theory
RF Network Analyzers
A11 Phase Lock: Comparing Phase and Frequency
The 10 MHz 1st IF signal from the A64 sampler is fed back to the A11 phase lock assembly.
The IF signal is amplified, limited, and filtered to produce a 10 MHz square wave by the
A11 phase lock assembly. The 10 MHz squarewave is then divided down to 1 MHz, and
applied to a phase/frequency detector that compares it to a crystal controlled 1 MHz signal
(PL REF) from the A12 reference assembly (see “A12 Reference: The Crystal Reference
Frequencies” on page 12-16). Any phase or frequency difference between these two signals
produces a proportional dc voltage.
Tuning the YIG Oscillator
The output of the phase/frequency detector is filtered to remove any 1 MHz feedthrough,
and is fed to an integrator. The output of the integrator is converted to a tune current. This
brings the appropriate YIG oscillator closer to the desired frequency, which in turn reduces
the phase/frequency detector output voltage. When the voltage is reduced to zero, and the
divided-down 1st IF frequency is equal to the 1 MHz reference frequency PL REF, phase
lock is achieved.
Phase Locked Sweep
When the source is phase locked to the synthesizer at the start frequency, the synthesizer
starts to sweep. The phase-locked loop forces the source to track the synthesizer,
maintaining a constant 10 MHz 1st IF signal.
The full sweep is generated in a series of subsweeps, by phase locking the source signal to
the harmonic multiples of the synthesizer. At the transitions between subsweeps, phase
lock is broken, the source is held at this frequency. Table 12-2 lists the subsweep
frequencies from the synthesizer and the source.
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