Service Guide 12-25
8719ET/20ET/22ET Theory of Operation
8719ES/20ES/22ES Receiver Theory
RF Network Analyzers
Part of the 1st IF signal from the R sampler is fed back to the A11 phase lock assembly to
complete the source phase-locked loop. The 1st IF from all three samplers goes to the
corresponding second converters. The A67 sampler is only used in option 400 instruments
and is only functional during measurements with a TRL calibration.
2nd LO Signal. The stable 2nd LO signal is produced in the A12 reference assembly by
phase locking and mixing a 39.984 MHz VCO with the 40 MHz VCXO to derive a
difference of 16 kHz. This is compared to a 16 kHz reference produced by dividing 40 MHz
by 2500. The phase-locked output of the 39.984 MHz oscillator is divided by 4 to provide
the 9.996 MHz 2nd LO signal.
A4/A5/A6 Second Converters. The 1st IF and the 2nd LO are mixed in the second
converter. The resulting difference frequency is a constant 4 kHz 2nd IF signal that retains
the amplitude and phase characteristics of the measured signal. The 2nd IF signals from
all three second converter assemblies are input to the A10 digital IF assembly.
A10 Digital IF
In this assembly, the 2nd IF signals from the A and B second converters go through a gain
stage. Signals less than −30 dB on these two signal paths are amplified by 24 dB to ensure
that they can be detected by the ADC (analog-to-digital converter). For troubleshooting
purposes, the gain can be forced on or off by using the service menus (refer to Chapter 8 ,
“Receiver Troubleshooting”). The R path signal is fixed at a level high enough to maintain
phase lock, and therefore requires no amplification.
All three signals are sampled at a 16 kHz rate set by a divided-down 4 MHz clock pulse
from the A12 reference assembly. The signals are sequentially multiplexed into the ADC,
where they are converted to digital form. The ADC conversions are triggered by timing
signals from the CPU or the synthesizer, or an external signal at the rear panel EXT TRIG
connector. The digitized data is serially clocked into the A7 CPU assembly to be processed
into magnitude and phase data.
The processed and formatted data is finally routed to the display, and to the GPIB for
remote operation. Refer to “Digital Control Theory” on page 12-9 and to the “Operating
Concepts” chapter of the user’s guide for more information on signal processing.
An additional input to the A10 assembly is the analog bus (ABUS), a built-in service tool
for testing analog circuits within the instrument. This is a single multiplexed line that
networks analog nodes throughout the instrument, or monitors an external input at the
rear panel AUX INPUT connector. It is controlled by the CPU, and used like an oscilloscope
or frequency counter to make internal voltage and frequency measurements.
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