Altera Cyclone V - Page 27

Chapter 2: Getting Started 2–15
Qsys Design Flow
November 2011 Altera Corporation Cyclone V Hard IP for PCI Express
User Guide
f For more information about Avalon interfaces, refer to the Avalon Interface
Specifications.
3. Connect the following Avalon Conduit interfaces using the technique described in
Step 1.
■ lmi
■ config_tl
■ power_mgmt
■ hip_status
■ rx_bar_be
■ tx_cred
■ hip_rst
■ reconfig_to_xcvr
■ reconfig_from_xcvr
■ int_msi
4. Follow these steps to connect the clocks:
a. In the Clock column right-click on the DUT
pld_clk interface and select
APPS.pld_clk_hip from the DUT.pld_clk Connections list.
b. To connect the APPS
pld_clk_hip interface to the DUT pld_clk interface,
right-click on APPS.pld_clk_hip and select DUT.pld_clk from the
APPS.pld_clk_hip Connections list.
c. To connect the DUT
coreclkout_hip interface to the APPS coreclkout_hip
interface, right-click on DUT.coreclkout_hip and select DUT.coreclkout_hip
from the DUT.coreclkout_hip Connections list. CHECK
d. To connect the DUT
coreclkout_hip interface to the APPS coreclkout_hip
interface, right-click on DUT.coreclkout_hip and select APPS.coreclkout_hip
from the DUT.coreclkout_hip Connections list.
5. To remove the default clock, on the System Contents tab, click clk_0 and then click
the X button.
6. To save your Qsys system, on the File menu select Save. Type
pcie_qsys in the
Save dialog box.