Altera Cyclone V - Page 62

5–10 Chapter 5: IP Core Interfaces
Avalon-ST TX Interface
Cyclone V Hard IP for PCI Express November 2011 Altera Corporation
tx_cred_fchipcons 6O
component
specific
Asserted for 1 cycle each time the Hard IP consumes a
credit. The 6 bits of this vector correspond to the following
6 types of credit types:
■ [5]: posted headers
■ [4]: posted data
■ [3]: non-posted header
■ [2]: non-posted data
■ [1]: completion header
■ [0]: completion data
During a single cycle, the Hard IP can consume either a
single header credit or both a header and a data credit.
tx_cred_fc_infinite 6O
component
specific
When asserted, indicates that the corresponding credit
type has infinite credits available and does not need to
calculate credit limits. The 6 bits of this vector correspond
to the following 6 types of credit types:
■ [5]: posted headers
■ [4]: posted data
■ [3]: non-posted header
■ [2]: non-posted data
■ [1]: completion header
■ [0]: completion data
tx_cred_hdrfccp 8O
component
specific
Header credit limit for the FC completions. Each credit is 20
bytes.
tx_cred_hdrfcnp 8O
component
specific
Header limit for the non-posted requests. Each credit is 20
bytes.
tx_cred_hdrfcp 8O
component
specific
Header credit limit for the FC posted writes. Each credit is
20 bytes.
ko_cpl_spc_header 8O
component
specific
The Application Layer can use this signal to build circuitry
to prevent RX buffer overflow for completion headers.
Endpoints must advertise infinite space for completion
headers; however, RX buffer space is finite.
ko_cpl_spc_header is a static signal that indicates the
total number of completion headers that can be stored in
the RX buffer.
ko_cpl_spc_data 12 O
component
specific
The Application Layer can use this signal to build circuitry
to prevent RX buffer overflow for completion data.
Endpoints must advertise infinite space for completion
data; however, RX buffer space is finite.
ko_cpl_spc_data is a static signal that reflects the total
number of 16 byte completion data units that can be stored
in the completion RX buffer. The total read data from all
outstanding MRd requests must be less than this value to
prevent RX FIFO overflow.
Note to Table 5–4:
(1) To be Avalon-ST compliant, your application have a readyLatency of 1 or 2 cycles.
Table 5–4. 64- or 128-Bit Avalon-ST TX Datapath (Part 3 of 3)
Signal Width Dir
Avalon-ST
Type
Description