Altera Cyclone V - Page 77

Chapter 5: IP Core Interfaces 5–25
Transaction Layer Configuration Space Signals
November 2011 Altera Corporation Cyclone V Hard IP for PCI Express
User Guide
cfg_slotcsr 16 O
cfg_slotcsr[31:16] is the Slot Control and
cfg_slotcsr[15:0] is the Slot Status of the PCI Express
capability structure. This register is only available in Root Port
mode.
Table 6–7 on
page 6–4
Table 6–8 on
page 6–4
cfg_linkcsr, 32 O
cfg_linkcsr[15:0] is the primary Link Control of the PCI
Express capability structure.
Table 6–7 on
page 6–4
Table 6–8 on
page 6–4
cfg_link2csr
cfg_link2csr[31:16]
is the secondary Link Status and
cfg_link2csr[15:0] is the secondary Link Control of the PCI
Express capability structure for Gen2 operation.
When
tl_cfg_addr=2 , tl_cfg_ctl returns the primary and
secondary Link Control registers,
{cfg_linkcsr[15:0],
cfg_lin2csr[15:0]}
, the primary Link Status register,
cfg_linkcsr[31:16] , is available on tl_cfg_sts[46:31] .
For Gen1 variants, the link bandwidth notification bit is always
set to 0.
Table 6–8 on
page 6–4
cfg_prmcsr_func<n> 16 O
Base/Primary Control and Status register for the PCI
Configuration Space.
Table 6–2 on
page 6–2
0x004 (Type 0)
Table 6–3 on
page 6–2
0x004 (Type 1)
cfg_rootcsr 8O
Root Control and Status register of the PCI-Express capability.
This register is only available in Root Port mode.
Table 6–7 on
page 6–4
Table 6–8 on
page 6–4
cfg_seccsr 16 O
Secondary bus Control and Status register of the PCI-Express
capability. This register is only available in Root Port mode.
Table 6–3 on
page 6–2
0x01C
cfg_secbus 8 O Secondary bus number. Available in Root Port mode.
Table 6–3 on
page 6–2
0x018
cfg_subbus 8 O Subordinate bus number. Available in Root Port mode.
Table 6–3 on
page 6–2
0x018
cfg_io_bas 20 O
The upper 20 bits of the IO limit registers of the Type1
Configuration Space. This register is only available in Root Port
mode.
Table 6–3 on
page 6–2
0x01C
cfg_io_lim 20 O
The upper 20 bits of the IO limit registers of the Type1
Configuration Space. This register is only available in Root Port
mode.
Table 6–8 on
page 6–4
0x01C
cfg_np_bas 12 O
The upper 12 bits of the memory base register of the Type1
Configuration Space. This register is only available in Root Port
mode.
Table 3–7 on
page 3–8
EXP ROM
cfg_np_lim 12 O
The upper 12 bits of the memory limit register of the Type1
Configuration Space. This register is only available in Root Port
mode.
Table 3–7 on
page 3–8
EXP ROM
Table 5–14. Configuration Space Register Descriptions (Part 2 of 3)
Register
Width Dir Description
Register
Reference