Altera Cyclone V - Page 8

1–2 Chapter 1: Datasheet
Features
Cyclone V Hard IP for PCI Express November 2011 Altera Corporation
■ Qsys walkthough demonstrating parameterization, design modules and
connectivity.
■ Easy to use:
■ Easy parameterization.
■ Substantial on-chip resource savings and guaranteed timing closure.
■ Easy adoption with no license requirement.
Table 1–1 summarizes the IP core’s features.
f The purpose of the Cyclone V Hard IP for PCI Express User Guide is to explain how to
use the Cyclone V Hard IP for PCI Express and not to explain the PCI Express
protocol. Although there is inevitable overlap between these two purposes, this
document should be used in conjunction with an understanding of the following PCI
Express specifications: PHY Interface for the PCI Express Architecture PCI Express 2.0 and
PCI Express Base Specification 2.1.
Table 1–1. Hard IP for PCI Express Features
Feature Avalon-ST Interface
MegaCore License Free
Endpoint Supported
Legacy Endpoint
(1)
Supported
Root port Supported
Gen1
(2)
×1, ×4
Multiple functions
Supports up to 8 functions for Endpoints and
Legacy Endpoints
MegaWizard Plug-In Manager design flow Supported
Qsys design flow Supported
64-bit Application Layer interface Supported
Transaction layer packet type (TLP)
(3)
All
Payload size 128–512 bytes
Number of tags supported for non-posted
requests
32 or 64
Low power mode using 62.5 MHz clock Supported
ECRC forwarding on RX and TX Supported
Number of MSI requests 16
MSI-X Supported
Legacy interrupts Supported
Expansion ROM Supported
Notes to Table 1–1:
(1) Not recommended for new designs.
(2) ×2 is supported by down training from ×4
(3) Refer to Appendix A, Transaction Layer Packet (TLP) Header Formats for the layout of TLP headers.