Altera Cyclone V - Page 94

6–6 Chapter 6: Register Descriptions
Correspondence between Configuration Space Registers and the PCIe Spec 2.1
Cyclone V Hard IP for PCI Express November 2011 Altera Corporation
0x3C0:0x3FC Port VC7 arbitration table (Reserved) Port Arbitration Table
0x400:0x7FC Reserved PCIe spec corresponding section name
0x800:0x834 Advanced Error Reporting AER (optional) Advanced Error Reporting Capability
0x838:0xFFF Reserved
Table 6-2. PCI Type 0 Configuration Space Header (Endpoints), Rev2.1 Spec: Type 0 Configuration Space Header
0x000 Device ID Vendor ID Type 0 Configuration Space Header
0x004 Status Command Type 0 Configuration Space Header
0x008 Class Code Revision ID Type 0 Configuration Space Header
0x00C 0x00 Header Type 0x00 Cache Line Size Type 0 Configuration Space Header
0x010 Base Address 0 Base Address Registers (Offset 10h - 24h)
0x014 Base Address 1 Base Address Registers (Offset 10h - 24h)
0x018 Base Address 2 Base Address Registers (Offset 10h - 24h)
0x01C Base Address 3 Base Address Registers (Offset 10h - 24h)
0x020 Base Address 4 Base Address Registers (Offset 10h - 24h)
0x024 Base Address 5 Base Address Registers (Offset 10h - 24h)
0x028 Reserved Type 0 Configuration Space Header
0x02C Subsystem Device ID Subsystem Vendor ID Type 0 Configuration Space Header
0x030 Expansion ROM base address Type 0 Configuration Space Header
0x034 Reserved Capabilities PTR Type 0 Configuration Space Header
0x038 Reserved Type 0 Configuration Space Header
0x03C 0x00 0x00 Interrupt Pin Interrupt Line Type 0 Configuration Space Header
Table 6-3. PCI Type 1 Configuration Space Header (Root Ports) , Rev2.1 Spec: Type 1 Configuration Space Header
0x000 Device ID Vendor ID Type 1 Configuration Space Header
0x004 Status Command Type 1 Configuration Space Header
0x008 Class Code Revision ID Type 1 Configuration Space Header
0x00C
BIST Header Type Primary Latency Timer Cache
Line Size
Type 1 Configuration Space Header
0x010 Base Address 0 Base Address Registers (Offset 10h/14h)
0x014 Base Address 1 Base Address Registers (Offset 10h/14h)
0x018
Secondary Latency Timer Subordinate Bus
Number Secondary Bus Number Primary Bus
Number
Secondary Latency Timer (Offset 1Bh)/Type 1
Configuration Space Header/ /Primary Bus Number
(Offset 18h)
0x01C Secondary Status I/O Limit I/O Base
Secondary Status Register (Offset 1Eh) / Type 1
Configuration Space Header
0x020 Memory Limit Memory Base Type 1 Configuration Space Header
0x024
Prefetchable Memory Limit Prefetchable Memory
Base
Prefetchable Memory Base/Limit (Offset 24h)
0x028 Prefetchable Base Upper 32 Bits Type 1 Configuration Space Header
0x02C Prefetchable Limit Upper 32 Bits Type 1 Configuration Space Header
0x030 I/O Limit Upper 16 Bits I/O Base Upper 16 Bits Type 1 Configuration Space Header
0x034 Reserved Capabilities PTR Type 1 Configuration Space Header
Table 6–9. Correspondence Configuration Space Registers and PCIe Base Specification Rev. 2.0 (Part 2 of 3)
Byte Address Hard IP Configuration Space Register Corresponding Section in PCIe Specification