Altera Cyclone V

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Chapter 6: Register Descriptions 6–7

Correspondence between Configuration Space Registers and the PCIe Spec 2.1

November 2011 Altera Corporation Cyclone V Hard IP for PCI Express

User Guide

0x038 Expansion ROM Base Address Type 1 Configuration Space Header

0x03C Bridge Control Interrupt Pin Interrupt Line Bridge Control Register (Offset 3Eh)

Table 6-4.MSI Capability Structure, Rev2.1 Spec: MSI Capability Structures

0x050 Message Control Next Cap Ptr Capability ID MSI and MSI-X Capability Structures

0x054 Message Address MSI and MSI-X Capability Structures

0x058 Message Upper Address MSI and MSI-X Capability Structures

0x05C Reserved Message Data MSI and MSI-X Capability Structures

Table 6-5. MSI-X Capability Structure, Rev2.1 Spec: MSI-X Capability Structures

0x68 Message Control Next Cap Ptr Capability ID MSI and MSI-X Capability Structures

0x6C MSI-X Table Offset BIR MSI and MSI-X Capability Structures

0x70 Pending Bit Array (PBA) Offset BIR MSI and MSI-X Capability Structures

Table 6-6. Power Management Capability Structure, Rev2.1 Spec

0x078 Capabilities Register Next Cap PTR Cap ID PCI Power Management Capability Structure

0x07C

Data PM Control/Status Bridge Extensions Power

Management Status & Control

PCI Power Management Capability Structure

Table 6-7 PCI Express Advanced Error Reporting Extended Capability Structure, Rev2.1 Spec: Advanced Error Reporting

Capability

0x800 PCI Express Enhanced Capability Header

Advanced Error Reporting Enhanced Capability

Header

0x804 Uncorrectable Error Status Register Uncorrectable Error Status Register

0x808 Uncorrectable Error Mask Register Uncorrectable Error Mask Register

0x80C Uncorrectable Error Severity Register Uncorrectable Error Severity Register

0x810 Correctable Error Status Register Correctable Error Status Register

0x814 Correctable Error Mask Register Correctable Error Mask Register

0x818 Advanced Error Capabilities and Control Register Advanced Error Capabilities and Control Register

0x81C Header Log Register Header Log Register

0x82C Root Error Command Root Error Command Register

0x830 Root Error Status Root Error Status Register

0x834

Error Source Identification Register Correctable

Error Source ID Register

Error Source Identification Register

Table 6–9. Correspondence Configuration Space Registers and PCIe Base Specification Rev. 2.0 (Part 3 of 3)

Byte Address Hard IP Configuration Space Register Corresponding Section in PCIe Specification

Altera Cyclone V - Page 95