Altera Cyclone V - Page 91

Chapter 6: Register Descriptions 6–3
Configuration Space Register Content
November 2011 Altera Corporation Cyclone V Hard IP for PCI Express
User Guide
Table 6–4 describes the MSI Capability structure.
Table 6–5 describes the MSI-X Capability structure.
0x020 Memory Limit Memory Base
0x024 Prefetchable Memory Limit Prefetchable Memory Base
0x028 Prefetchable Base Upper 32 Bits
0x02C Prefetchable Limit Upper 32 Bits
0x030 I/O Limit Upper 16 Bits I/O Base Upper 16 Bits
0x034 Reserved
Capabilities
Pointer
0x038 Expansion ROM Base Address
0x03C
Bridge Control Interrupt Pin Interrupt Line
Note to Table 6–3:
(1) Refer to Table 6–9 on page 6–5 for a comprehensive list of correspondences between the Configuration Space registers and the PCI Express
Base Specification 2.0.
Table 6–3. PCI Type 1 Configuration Space Header (Root Ports) (Part 2 of 2), Rev2.1 Spec: Type 1 Configuration Space
Header
Byte Offset 31:24 23:16 15:8 7:0
Table 6–4. MSI Capability Structure, Rev2.1 Spec: MSI Capability Structures
Byte Offsets
(1)
31:24 23:16 15:8 7:0
0x050
Message Control
Configuration MSI Control Status Register Field
Descriptions
Next Cap Ptr Capability ID
0x054 Message Address
0x058 Message Upper Address
0x05C Reserved Message Data
Note to Table 6–4:
(1) Specifies the byte offset within Cyclone V Hard IP for PCI Express IP core’s address space.
(2) Refer to Table 6–9 on page 6–5 for a comprehensive list of correspondences between the Configuration Space registers and the PCI Express
Base Specification 2.0.
Table 6–5. MSI-X Capability Structure, Rev2.1 Spec: MSI-X Capability Structures
Byte Offset 31:24 23:16 15:8 7:3 2:0
0x068
Message Control Next Cap Ptr Capability ID
0x06C MSI-X Table Offset
Pending
Bit Array
(PBA)
Offset
Note to Table 6–5:
(1) Refer to Table 6–9 on page 6–5 for a comprehensive list of correspondences between the Configuration Space registers and the PCI Express
Base Specification 2.0.