Keysight N9040B Option 508 - Page 66

66 Keysight Technologies N9040B UXA Signal Analyzer Service Guide
Boot Up and Initialization Troubleshooting
Potential Problems During Boot Process
Table 2-2 Initial Alignments
Alignment Description Most Probable Hardware
Failure
Related Hardware
DDS Synth Fast Port Skew Training A14 Synthesizer
DDS Synthesizer YTO Pretune DAC A14 Synthesizer A16 Reference board is not
providing correct 100 MHz or
4.8 GHz signals.
A20 YTO output power low.
VCXO Loop Bandwidth
Adjusts gain of the PLL loop amplifier. Uses the 10 MHz
internal reference
A16 Reference
Second LO Loop Bandwidth A2 Analog IF
Second LO Saw Peak A16 Reference
Ext Mix LO Alignment Algorithm
AIF 255 ADC Setup Alignment Algorithm Wide Band Analog IF or
Wideband Digital IF.
AIF 255 ADC Clock Alignment Algorithm
AIF 255 Flex Circuit Cable Test Algorithm W56 or W57 Flex circuit
cable
Dither Level Algorithm A3 Digital IF
LO Nulling Simplex MB Alignment Algorithm A13 Front End, Uses narrow
BW switched filter.
LO Nulling Simplex WB Alignment Algorithm A13 Front End, Uses wide
BW switched filter.
AIF LC Wide Prefilter Passband Tuning
Algorithm
A2 Analog IF
AIF LC Wide Prefilter Passband Fine Tuning
Algorithm
A2 Analog IF
AIF LC Narrow Prefilter Passband Tuning
Algorithm
A2 Analog IF
AIF LC Narrow Prefilter Passband Fine Tuning
Algorithm
A2 Analog IF
AIF Xtal Wide Prefilter Passband Tuning
Algorithm
A2 Analog IF A3 Digital IF or
A16 Reference
AIF Xtal Narrow Prefilter Passband Tuning
Algorithm
A2 Analog IF