230
CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2
Table 9-7. 8-Bit Timer/Event Counter 2 Interval Time
Minimum Interval Time Maximum Interval Time Resolution
MCS = 1 MCS = 0 MCS = 1 MCS = 0 MCS = 1 MCS = 0
0000 TI2 input cycle 2
8
× TI2 input cycle TI2 input edge cycle
0001 TI2 input cycle 2
8
× TI2 input cycle TI2 input edge cycle
2 × 1/fX 2
2
× 1/fX 2
9
× 1/fX 2
10
× 1/fX 2 × 1/fX 2
2
× 1/fX
(400 ns) (800 ns) (102.4
µ
s) (204.8
µ
s) (400 ns) (800 ns)
2
2
× 1/fX 2
3
× 1/fX 2
10
× 1/fX 2
11
× 1/fX 2
2
× 1/fX 2
3
× 1/fX
(800 ns) (1.6
µ
s) (204.8
µ
s) (409.6
µ
s) (800 ns) (1.6
µ
s)
2
3
× 1/fX 2
4
× 1/fX 2
11
× 1/fX 2
12
× 1/fX 2
3
× 1/fX 2
4
× 1/fX
(1.6
µ
s) (3.2
µ
s) (409.6
µ
s) (819.2
µ
s) (1.6
µ
s) (3.2
µ
s)
2
4
× 1/fX 2
5
× 1/fX 2
12
× 1/fX 2
13
× 1/fX 2
4
× 1/fX 2
5
× 1/fX
(3.2
µ
s) (6.4
µ
s) (819.2
µ
s) (1.64 ms) (3.2
µ
s) (6.4
µ
s)
2
5
× 1/fX 2
6
× 1/fX 2
13
× 1/fX 2
14
× 1/fX 2
5
× 1/fX 2
6
× 1/fX
(6.4
µ
s) (12.8
µ
s) (1.64 ms) (3.28 ms) (6.4
µ
s) (12.8
µ
s)
2
6
× 1/fX 2
7
× 1/fX 2
14
× 1/fX 2
15
× 1/fX 2
6
× 1/fX 2
7
× 1/fX
(12.8
µ
s) (25.6
µ
s) (3.28 ms) (6.55 ms) (12.8
µ
s) (25.6
µ
s)
2
7
× 1/fX 2
8
× 1/fX 2
15
× 1/fX 2
16
× 1/fX 2
7
× 1/fX 2
8
× 1/fX
(25.6
µ
s) (51.2
µ
s) (6.55 ms) (13.1 ms) (25.6
µ
s) (51.2
µ
s)
2
8
× 1/fX 2
9
× 1/fX 2
16
× 1/fX 2
17
× 1/fX 2
8
× 1/fX 2
9
× 1/fX
(51.2
µ
s) (102.4
µ
s) (13.1 ms) (26.2 ms) (51.2
µ
s) (102.4
µ
s)
2
9
× 1/fX 2
10
× 1/fX 2
17
× 1/fX 2
18
× 1/fX 2
9
× 1/fX 2
10
× 1/fX
(102.4
µ
s) (204.8
µ
s) (26.2 ms) (52.4 ms) (102.4
µ
s) (204.8
µ
s)
2
11
× 1/fX 2
12
× 1/fX 2
19
× 1/fX 2
20
× 1/fX 2
11
× 1/fX 2
12
× 1/fX
(409.6
µ
s) (819.2
µ
s) (104.9 ms) (209.7 ms) (409.6
µ
s) (819.2
µ
s)
Other than above Setting prohibited
Remarks 1. f
X : Main system clock oscillation frequency
2. MCS : Bit 0 of oscillation mode selection register (OSMS)
3. TCL14 to TCL17 : Bits 4 to 7 of timer clock select register 1 (TCL1)
4. Values in parentheses when operated at f
X = 5.0 MHz
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
TCL17 TCL16 TCL15 TCL14
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