NEC PD78052 - Square-Wave Output Ranges When 2-Channel 8-Bit Timer; Event Counters (TM1 and TM2 Are Used as 16-Bit Timer;Event Counter

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CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2
(3) Square-wave output operation
Operates as square wave output with any selected frequency at intervals of the count value preset to 8-bit
compare registers 10 and 20 (CR10, CR20). When setting the count value, set the value of higher 8 bits to
CR20 and the value of lower 8 bits to CR10.
The TO2/P32 pin output status is reversed at intervals of the count value preset to CR10 and CR20 by setting
bit 4 (TOE2) of the 8-bit timer output control register (TOC1) to 1. This enables a square wave with any selected
frequency to be output.
Table 9-10. Square-Wave Output Ranges when 2-Channel 8-Bit Timer/Event Counters
(TM1 and TM2) are Used as 16-Bit Timer/Event Counter
Minimum Pulse Width Maximum Pulse Width Resolution
MCS = 1 MCS = 0 MCS = 1 MCS = 0 MCS = 1 MCS = 0
2 × 1/f
X 2
2
× 1/fX 2
17
× 1/fX 2
18
× 1/fX 2 × 1/fX 2
2
× 1/fX
(400 ns) (800 ns) (26.2 ms) (52.4 ms) (400 ns) (800 ns)
2
2
× 1/fX 2
3
× 1/fX 2
18
× 1/fX 2
19
× 1/fX 2
2
× 1/fX 2
3
× 1/fX
(800 ns) (1.6 µ s) (52.4 ms) (104.9 ms) (800 ns) (1.6 µ s)
2
3
× 1/fX 2
4
× 1/fX 2
19
× 1/fX 2
20
× 1/fX 2
3
× 1/fX 2
4
× 1/fX
(1.6 µ s) (3.2 µ s) (104.9 ms) (209.7 ms) (1.6 µ s) (3.2 µ s)
2
4
× 1/fX 2
5
× 1/fX 2
20
× 1/fX 2
21
× 1/fX 2
4
× 1/fX 2
5
× 1/fX
(3.2 µ s) (6.4 µ s) (209.7 ms) (419.4 ms) (3.2 µ s) (6.4 µ s)
2
5
× 1/fX 2
6
× 1/fX 2
21
× 1/fX 2
22
× 1/fX 2
5
× 1/fX 2
6
× 1/fX
(6.4 µ s) (12.8 µ s) (419.4 ms) (838.9 ms) (6.4 µ s) (12.8 µ s)
2
6
× 1/fX 2
7
× 1/fX 2
22
× 1/fX 2
23
× 1/fX 2
6
× 1/fX 2
7
× 1/fX
(12.8 µ s) (25.6 µ s) (838.9 ms) (1.7 s) (12.8 µ s) (25.6 µ s)
2
7
× 1/fX 2
8
× 1/fX 2
23
× 1/fX 2
24
× 1/fX 2
7
× 1/fX 2
8
× 1/fX
(25.6 µ s) (51.2 µ s) (1.7 s) (3.4 s) (25.6 µ s) (51.2 µ s)
2
8
× 1/fX 2
9
× 1/fX 2
24
× 1/fX 2
25
× 1/fX 2
8
× 1/fX 2
9
× 1/fX
(51.2 µ s) (102.4 µ s) (3.4 s) (6.7 s) (51.2 µ s) (102.4 µ s)
2
9
× 1/fX 2
10
× 1/fX 2
25
× 1/fX 2
26
× 1/fX 2
9
× 1/fX 2
10
× 1/fX
(102.4 µ s) (204.8 µ s) (6.7 s) (13.4 s) (102.4 µ s) (204.8 µ s)
2
11
× 1/fX 2
12
× 1/fX 2
27
× 1/fX 2
28
× 1/fX 2
11
× 1/fX 2
12
× 1/fX
(409.6 µ s) (819.2 µ s) (26.8 s) (53.7 s) (409.6 µ s) (819.2 µ s)
Remarks 1. f
X : Main system clock oscillation frequency
2. MCS : Oscillation mode selection register (OSMS) bit 0
3. Values in parentheses when operated at f
X = 5.0 MHz.