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NEC PD78052 - Appendix A Differences between Pd78054, 78054 Y Subseries and Pd78058 F, 78058 Fy Subseries
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577
APPENDIX A DIFFERENCES BETWEEN
µ
PD78054, 78054Y SUBSERIES
AND
µ
PD78058F, 78058FY SUBSERIES
Table A-1 shows the major differences between the
µ
PD78054, 78054Y Subseries and
µ
PD78058F, 78058FY
Subseries.
576
578
Table of Contents
Main Page
Default Chapter
6
Regional Information
6
Major Revisions in this Edition
7
Table of Contents
17
CHAPTER 1 GENERAL ( PD78054 Subseries)
37
Features
37
Applications
38
Ordering Information
38
Quality Grade
39
Pin Configuration (Top View)
40
Series Expansion
43
Block Diagram
45
Outline of Function
46
Mask Options of Mask ROM Versions
48
Differences between Standard Quality Grade Products and (A) Products
48
Mask Options
48
CHAPTER 2 GENERAL ( PD78054Y Subseries)
49
Features
49
Applications
50
Ordering Information
50
Quality Grade
50
Pin Configuration (Top View)
51
Series Expansion
54
Block Diagram
56
Outline of Function
57
Mask Options
58
CHAPTER 3 PIN FUNCTION ( PD78054 Subseries)
59
Pin Function List
59
Normal Operating Mode Pins
59
PROM Programming Mode Pins (PROM Versions Only)
63
Description of Pin Functions
64
P00 to P07 (Port 0)
64
P10 to P17 (Port 1)
65
P20 to P27 (Port 2)
65
P30 to P37 (Port 3)
66
P40 to P47 (Port 4)
67
P50 to P57 (Port 5)
67
P60 to P67 (Port 6)
67
P70 to P72 (Port 7)
68
P120 to P127 (Port 12)
69
P130 and P131 (Port 13)
69
Av Ref0
69
Av Ref1
69
Av DD
70
Av Ss
70
Reset
70
X1 and X2
70
XT1 and XT2
70
VDD
70
Vss
70
PP (PROM Versions Only)
70
IC (Mask ROM Version Only)
70
Input/Output Circuits and Recommended Connection of Unused Pins
71
Pin Input/Output Circuit Types
71
Pin Input/Output Circuit of List
73
CHAPTER 4 PIN FUNCTION ( PD78054Y Subseries)
75
Pin Function List
75
Normal Operating Mode Pins
75
PROM Programming Mode Pins (PROM Versions Only)
79
Description of Pin Functions
80
P00 to P07 (Port 0)
80
P10 to P17 (Port 1)
81
P20 to P27 (Port 2)
81
P30 to P37 (Port 3)
82
P40 to P47 (Port 4)
82
P50 to P57 (Port 5)
83
P60 to P67 (Port 6)
83
P70 to P72 (Port 7)
84
P120 to P127 (Port 12)
84
P130 and P131 (Port 13)
85
Av Ref0
85
Av Ref1
85
Av DD
85
Av Ss
85
Reset
85
X1 and X2
86
XT1 and XT2
86
VDD
86
Vss
86
PP (PROM Versions Only)
86
IC (Mask ROM Version Only)
86
Input/Output Circuits and Recommended Connection of Unused Pins
87
Pin Input/Output Circuit Types
87
Pin Input/Output Circuit of List
89
Chapter 5 Cpu Architecture
91
Memory Spaces
91
Memory Map ( PD78052, 78052Y)
91
Memory Map ( PD78053, 78053Y)
92
Memory Map ( PD78054, 78054Y)
93
Memory Map ( PD78P054)
94
Memory Map ( PD78055, 78055Y)
95
Memory Map ( PD78056, 78056Y)
96
Memory Map ( PD78058, 78058Y)
97
Memory Map ( PD78P058, PD78P058Y)
98
Internal Program Memory Space
99
Internal ROM Capacity
99
Vector Table
99
External Memory Space
100
Internal Data Memory Space
100
Special Function Register (SFR) Area
100
Internal High-Speed RAM Capacity
100
Data Memory Addressing
101
Data Memory Addressing ( PD78053, 78053Y)
102
Data Memory Addressing ( PD78054, 78054Y)
103
Data Memory Addressing ( PD78P054)
104
Data Memory Addressing ( PD78055, 78055Y)
105
Data Memory Addressing ( PD78056, 78056Y)
106
Data Memory Addressing ( PD78058, 78058Y)
107
Data Memory Addressing ( PD78P058, 78P058Y)
108
Program Status Word Configuration
109
Processor Registers
109
Control Registers
109
Program Counter Configuration
109
Internal High-Speed RAM Area
110
Data to be Reset from Stack Memory
111
Data to be Saved to Stack Memory
111
Stack Pointer Configuration
111
Correspondent Table of Absolute Addresses in the General Registers
112
General Registers
112
General Register Configuration
113
Special Function Register (SFR)
114
Special-Function Register List
115
Instruction Address Addressing
118
Relative Addressing
118
Immediate Addressing
119
Table Indirect Addressing
120
Register Addressing
120
Operand Address Addressing
121
Implied Addressing
121
Register Addressing
122
Direct Addressing
123
Short Direct Addressing
124
Special-Function Register (SFR) Addressing
125
Register Indirect Addressing
126
Based Addressing
127
Based Indexed Addressing
128
Stack Addressing
128
Chapter 6 Port Functions
129
Port Functions
129
Port Types
129
Port Functions ( PD78054 Subseries)
130
Port Functions ( PD78054Y Subseries)
132
Port Configuration
134
Port 0
134
P00 and P07 Block Diagram
135
P01 to P06 Block Diagram
135
Port 1
136
P10 to P17 Block Diagram
136
Port 2 ( PD78054 Subseries)
137
P20, P21, P23 to P26 Block Diagram
137
P22 and P27 Block Diagram
138
Port 2 ( PD78054Y Subseries)
139
P20, P21, P23 to P26 Block Diagram
139
P22 and P27 Block Diagram
140
Port 3
141
P30 to P37 Block Diagram
141
Block Diagram of Falling Edge Detection Circuit
142
Port 4
142
P40 to P47 Block Diagram
142
Port 5
143
P50 to P57 Block Diagram
143
Port 6
144
P60 to P63 Block Diagram
145
P64 to P67 Block Diagram
145
Port 7
146
P70 Block Diagram
146
P71 and P72 Block Diagram
147
Port 12
148
P120 to P127 Block Diagram
148
Port 13
149
P130 and P131 Block Diagram
149
Port Function Control Registers
150
Port Mode Register and Output Latch Settings When Using Dual-Functions
151
Port Mode Register Format
152
Pull-Up Resistor Option Register Format
153
Memory Expansion Mode Register Format
154
Key Return Mode Register Format
155
Port Function Operations
156
Reading from Input/Output Port
156
Writing to Input/Output Port
156
Comparison between Mask ROM Version and PROM Version
157
Operations on Input/Output Port
157
Selection of Mask Option
157
Chapter 7 Clock Generator
159
Clock Generator Functions
159
Clock Generator Configuration
159
Block Diagram of Clock Generator
160
Clock Generator Control Register
161
Subsystem Clock Feedback Resistor
161
Processor Clock Control Register Format
162
Relationship between CPU Clock and Minimum Instruction Execution Time
163
Oscillation Mode Selection Register Format
164
Main System Clock When Writing to OSMS
164
External Circuit of Main System Clock Oscillator
165
System Clock Oscillator
165
Main System Clock Oscillator
165
Examples of Incorrect Oscillator Connection
166
Scaler
168
When no Subsystem Clocks Are Used
168
Clock Generator Operations
169
External Circuit of Subsystem Clock Oscillator
166
Subsystem Clock Oscillator
166
Main System Clock Operations
170
Main System Clock Stop Function
170
Subsystem Clock Operations
171
Changing System Clock and CPU Clock Settings
171
Time Required for Switchover between System Clock and CPU Clock
171
System Clock and CPU Clock Switching Procedure
173
Chapter 8 16-Bit Timer/Event Counter
175
Outline of Timers Incorporated in the PD78054, 78054Y Subseries
175
Timer/Event Counter Operations
176
16-Bit Timer/Event Counter Functions
177
Bit Timer/Event Counter Interval Times
177
Bit Timer/Event Counter Square-Wave Output Ranges
178
16-Bit Timer/Event Counter Configuration
179
Bit Timer/Event Counter Block Diagram
179
Bit Timer/Event Counter Output Control Circuit Block Diagram
180
INTP0/TI00 Pin Valid Edge and CR00 Capture Trigger Valid Edge
181
16-Bit Timer/Event Counter Control Registers
182
Timer Clock Selection Register 0 Format
183
Bit Timer Mode Control Register Format
185
Capture/Compare Control Register 0 Format
186
Bit Timer Output Control Register Format
187
Port Mode Register 3 Format
188
External Interrupt Mode Register 0 Format
189
Sampling Clock Select Register Format
190
16-Bit Timer/Event Counter Operations
191
Control Register Settings for Interval Timer Operation
191
Interval Timer Operations
191
Interval Timer Configuration Diagram
192
PWM Output Operations
193
Interval Timer Operation Timings
192
Bit Timer/Event Counter Interval Times
193
Control Register Settings for PWM Output Operation
194
Example of D/A Converter Configuration with PWM Output
195
TV Tuner Application Circuit Example
195
PPG Output Operations
196
Control Register Settings for PPG Output Operation
196
Pulse Width Measurement Operations
197
Timing of Pulse Width Measurement Operation by Free-Running Counter and One Capture Register (with both Edges Specified)
198
Configuration Diagram for Pulse Width Measurement by Free-Running Counter
198
Control Register Settings for Two Pulse Width Measurements with Free-Running Counter
199
Two Capture Registers (with Rising Edge Specified)
202
Control Register Settings for Pulse Width Measurement by Means of Restart
203
External Event Counter Operation
204
Control Register Settings in External Event Counter Mode
204
External Event Counter Configuration Diagram
205
Square-Wave Output Operation
206
External Event Counter Operation Timings (with Rising Edge Specified)
205
Control Register Settings in Square-Wave Output Mode
206
Bit Timer/Event Count Square-Wave Output Ranges
207
One-Shot Pulse Output Operation
208
Square-Wave Output Operation Timing
207
Timing of One-Shot Pulse Output Operation Using Software Trigger
209
Control Register Settings for One-Shot Pulse Output Operation Using External Trigger
210
16-Bit Timer/Event Counter Operating Precautions
212
Bit Timer Register Start Timing
212
Timings after Change of Compare Register During Timer Count Operation
212
Capture Register Data Retention Timing
213
Operation Timing of OVF0 Flag
214
Chapter 9 8-Bit Timer/Event Counters 1 and 2
215
8-Bit Timer/Event Counters 1 and 2 Functions
215
8-Bit Timer/Event Counter Mode
215
Bit Timer/Event Counters 1 and 2 Interval Times
216
Bit Timer/Event Counters 1 and 2 Square-Wave Output Ranges
217
16-Bit Timer/Event Counter Mode
218
8-Bit Timer/Event Counters 1 and 2 Configurations
220
Bit Timer/Event Counters 1 and 2 Block Diagram
221
Block Diagram of 8-Bit Timer/Event Counter Output Control Circuit 1
222
Block Diagram of 8-Bit Timer/Event Counter Output Control Circuit 2
222
8-Bit Timer/Event Counters 1 and 2 Control Registers
223
Timer Clock Select Register 1 Format
224
Bit Timer Mode Control Register 1 Format
225
Bit Timer Output Control Register Format
226
Port Mode Register 3 Format
227
8-Bit Timer/Event Counters 1 and 2 Operations
228
8-Bit Timer/Event Counter Mode
228
Interval Timer Operation Timings
228
Bit Timer/Event Counter 1 Interval Time
229
Bit Timer/Event Counter 2 Interval Time
230
External Event Counter Operation Timings (with Rising Edge Specified)
231
Bit Timer/Event Counters 1 and 2 Square-Wave Output Ranges
232
Square-Wave Output Operation Timing
233
16-Bit Timer/Event Counter Mode
234
Interval Timer Operation Timing
234
Interval Times When 2-Channel 8-Bit Timer/ Event Counters (TM1 and TM2) Are Used as 16-Bit Timer/Event Counter
235
External Event Counter Operation Timings (with Rising Edge Specified)
236
Square-Wave Output Ranges When 2-Channel 8-Bit Timer/ Event Counters (TM1 and TM2 Are Used as 16-Bit Timer/Event Counter
237
Bit Timer Registers 1 and 2 Start Timing
238
Square-Wave Output Operation Timing
238
Cautions on 8-Bit Timer/Event Counters 1 and 2
238
Event Counter Operation Timing
239
Timing after Compare Register Change During Timer Count Operation
239
Chapter 10 Watch Timer
241
Watch Timer Functions
241
Interval Timer Interval Time
241
Watch Timer Configuration
242
Watch Timer Control Registers
242
Watch Timer Block Diagram
243
Timer Clock Select Register 2 Format
244
Watch Timer Mode Control Register Format
245
Interval Timer Interval Time
246
Watch Timer Operations
246
Watch Timer Operation
246
Interval Timer Operation
246
Chapter 11 Watchdog Timer
247
Watchdog Timer Functions
247
Watchdog Timer Runaway Detection Times
247
Interval Times
248
Watchdog Timer Configuration
249
Watchdog Timer Block Diagram
249
Watchdog Timer Control Registers
250
Timer Clock Select Register 2 Format
251
Watchdog Timer Mode Register Format
252
Watchdog Timer Operations
253
Watchdog Timer Operation
253
Watchdog Timer Runaway Detection Times
253
Interval Timer Interval Time
254
Interval Timer Operation
254
Chapter 12 Clock Output Control Circuit
255
Clock Output Control Circuit Functions
255
Remote Controlled Output Application Example
255
Clock Output Control Circuit Configuration
256
Clock Output Control Circuit Block Diagram
256
Clock Output Function Control Registers
257
Timer Clock Select Register 0 Format
258
Port Mode Register 3 Format
259
Chapter 13 Buzzer Output Control Circuit
261
Buzzer Output Control Circuit Functions
261
Buzzer Output Control Circuit Configuration
261
Buzzer Output Control Circuit Block Diagram
261
Buzzer Output Function Control Registers
262
Timer Clock Select Register 2 Format
263
Port Mode Register 3 Format
264
Chapter 14 A/D Converter
265
A/D Converter Functions
265
A/D Converter Configuration
265
A/D Converter Block Diagram
266
A/D Converter Control Registers
269
A/D Converter Mode Register Format
270
A/D Converter Input Select Register Format
271
External Interrupt Mode Register 1 Format
272
A/D Converter Operations
273
Basic Operations of A/D Converter
273
A/D Converter Basic Operation
274
Input Voltage and Conversion Results
275
Relations between Analog Input Voltage and A/D Conversion Result
275
A/D Converter Operating Mode
276
A/D Conversion by Hardware Start
276
A/D Conversion by Software Start
277
A/D Converter Cautions
278
Example of Method of Reducing Current Dissipation in Standby Mode
278
Analog Input Pin Disposition
279
A/D Conversion End Interrupt Request Generation Timing
280
Chapter 15 D/A Converter
281
D/A Converter Functions
281
D/A Converter Configuration
282
D/A Converter Block Diagram
282
D/A Converter Control Registers
284
D/A Converter Mode Register Format
284
Operations of D/A Converter
285
Cautions Related to D/A Converter
286
Use Example of Buffer Amplifier
286
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( PD78054 Subseries)
287
Differences between Channels 0, 1, and 2
287
Serial Interface Channel 0 Functions
288
Serial Bus Interface (SBI) System Configuration Example
289
Serial Interface Channel 0 Configuration
290
Serial Interface Channel 0 Block Diagram
291
Serial Interface Channel 0 Control Registers
294
Timer Clock Select Register 3 Format
295
Serial Operating Mode Register 0 Format
296
Serial Bus Interface Control Register Format
298
Interrupt Timing Specify Register Format
300
Serial Interface Channel 0 Operations
301
Operation Stop Mode
301
3-Wire Serial I/O Mode Operation
302
RELT and CMDT Operations
305
Wire Serial I/O Mode Timings
305
Circuit of Switching in Transfer Bit Order
306
SBI Mode Operation
307
Example of Serial Bus Configuration with SBI
307
SBI Transfer Timings
309
Bus Release Signal
310
Command Signal
310
Addresses
311
Slave Selection with Address
311
Commands
312
Data
312
Acknowledge Signal
313
BUSY and READY Signals
314
RELT and CMDD Operations (Slave)
319
RELT, CMDT, RELD, and CMDD Operations (Master)
319
ACKT Operation
320
ACKE Operations
321
ACKD Operations
322
BSYE Operation
322
Various Signals in SBI Mode
323
Pin Configuration
325
Address Transmission from Master Device to Slave Device (WUP = 1)
327
Command Transmission from Master Device to Slave Device
328
Data Transmission from Master Device to Slave Device
329
Data Transmission from Slave Device to Master Device
330
2-Wire Serial I/O Mode Operation
333
Serial Bus Configuration Example Using 2-Wire Serial I/O Mode
333
Wire Serial I/O Mode Timings
337
RELT and CMDT Operations
338
SCK0/P27 Pin Configuration
339
SCK0/P27 Pin Output Manipulation
339
CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78054Y Subseries)
341
Differences between Channels 0, 1, and 2
341
Serial Interface Channel 0 Functions
342
Serial Interface Channel 0 Configuration
344
Serial Interface Channel 0 Block Diagram
345
Serial Interface Channel 0 Interrupt Request Signal Generation
347
Serial Interface Channel 0 Control Registers
348
Timer Clock Select Register 3 Format
349
Serial Operating Mode Register 0 Format
351
Serial Bus Interface Control Register Format
352
Interrupt Timing Specify Register Format
354
Serial Interface Channel 0 Operations
356
Operation Stop Mode
356
3-Wire Serial I/O Mode Operation
357
RELT and CMDT Operations
359
Wire Serial I/O Mode Timings
359
Circuit of Switching in Transfer Bit Order
360
2-Wire Serial I/O Mode Operation
361
Serial Bus Configuration Example Using 2-Wire Serial I/O Mode
361
Wire Serial I/O Mode Timings
365
RELT and CMDT Operations
366
I 2 C Bus Mode Operation
367
Address
369
Start Condition
369
Transfer Direction Specification
369
Acknowledge Signal
370
Stop Condition
370
Wait Signal
371
Pin Configuration
377
Data Transmission from Master to Slave (both Master and Slave Selected 9-Clock Wait)
379
Data Transmission from Slave to Master (both Master and Slave Selected 9-Clock Wait)
383
Cautions on Use of I C Bus Mode
385
Start Condition Output
385
Slave Wait Release (Transmission)
386
Slave Wait Release (Reception)
387
Restrictions in I 2 C Bus Mode
388
SCK0/SCL/P27 Pin Configuration
390
SCK0/SCL/P27 Pin Output Manipulation
390
Logic Circuit of SCL Signal
391
Chapter 18 Serial Interface Channel 1
393
Serial Interface Channel 1 Functions
393
Serial Interface Channel 1 Configuration
394
Serial Interface Channel 1 Block Diagram
395
Serial Interface Channel 1 Control Registers
397
Timer Clock Select Register 3 Format
398
Serial Operation Mode Register 1 Format
399
Automatic Data Transmit/Receive Control Register Format
400
Automatic Data Transmit/Receive Interval Specify Register Format
401
Serial Interface Channel 1 Operations
405
Operation Stop Mode
405
3-Wire Serial I/O Mode Operation
406
Wire Serial I/O Mode Timings
407
Circuit of Switching in Transfer Bit Order
408
3-Wire Serial I/O Mode Operation with Automatic Transmit/Receive Function
409
Basic Transmission/Reception Mode Operation Timings
417
Basic Transmission/Reception Mode Flowchart
418
Basic Transmission Mode Operation Timings
421
Basic Transmission Mode Flowchart
422
Repeat Transmission Mode Operation Timing
425
Repeat Transmission Mode Flowchart
426
Automatic Transmission/Reception Suspension and Restart
429
System Configuration When the Busy Control Option Is Used
430
Operation Timings When Using Busy Control Option (BUSY0 = 0)
431
Busy Signal and Wait Cancel (When BUSY0 = 0)
432
Operation Timings When Using Busy & Strobe Control Option (BUSY0 = 0)
433
Automatic Data Transmit/Receive Interval
435
Interval Timing through CPU Processing (When the Internal Clock Is Operating)
436
Operation Timing with Automatic Data Transmit/Receive Function Performed by Internal Clock
436
Interval Timing through CPU Processing (When the External Clock Is Operating)
437
Chapter 19 Serial Interface Channel 2
439
Serial Interface Channel 2 Functions
439
Serial Interface Channel 2 Configuration
440
Serial Interface Channel 2 Block Diagram
441
Baud Rate Generator Block Diagram
442
Serial Interface Channel 2 Control Registers
444
Serial Operating Mode Register 2 Format
444
Asynchronous Serial Interface Mode Register Format
445
Serial Interface Channel 2 Operating Mode Settings
446
Asynchronous Serial Interface Status Register Format
447
Baud Rate Generator Control Register Format
448
Relation between Main System Clock and Baud Rate
450
Serial Interface Channel 2 Operation
452
Operation Stop Mode
452
Asynchronous Serial Interface (UART) Mode
454
Relation between Main System Clock and Baud Rate
459
Relation between ASCK Pin Input Frequency and Baud Rate (When BRGC Is Set to 00H)
460
Asynchronous Serial Interface Transmit/Receive Data Format
461
Asynchronous Serial Interface Transmission Completion Interrupt Request Generation Timing
463
Receive Error Causes
465
3-Wire Serial I/O Mode
467
Wire Serial I/O Mode Timing
472
Circuit of Switching in Transfer Bit Order
473
Limitations When UART Mode Is Used
474
Receive Error Timing
465
Reception Completion Interrupt Request Generation Timing (When ISRM = 1)
474
Receive Buffer Register Read Disable Period
475
Chapter 20 Real-Time Output Port
477
Real-Time Output Port Functions
477
Real-Time Output Port Configuration
478
Real-Time Output Port Block Diagram
478
Real-Time Output Buffer Register Configuration
479
Operation in Real-Time Output Buffer Register Manipulation
479
Real-Time Output Port Control Registers
480
Port Mode Register 12 Format
480
Real-Time Output Port Mode Register Format
480
Real-Time Output Port Control Register Format
481
Real-Time Output Port Operating Mode and Output Trigger
481
Chapter 21 Interrupt and Test Functions
483
Interrupt Function Types
483
Interrupt Sources and Configuration
484
Interrupt Source List
484
Basic Configuration of Interrupt Function
486
Interrupt Function Control Registers
488
Various Flags Corresponding to Interrupt Request Sources
488
Interrupt Request Flag Register Format
489
Interrupt Mask Flag Register Format
490
Priority Specify Flag Register Format
491
External Interrupt Mode Register 0 Format
492
External Interrupt Mode Register 1 Format
493
Sampling Clock Select Register Format
494
Noise Eliminator Input/Output Timing (During Rising Edge Detection)
495
Program Status Word Configuration
496
Interrupt Servicing Operations
497
Non-Maskable Interrupt Request Acknowledge Operation
497
Flowchart of Generation from Non-Maskable Interrupt Request to Acknowledgment
498
Non-Maskable Interrupt Request Acknowledge Timing
498
Non-Maskable Interrupt Request Acknowledge Operation
499
Maskable Interrupt Request Acknowledge Operation
500
Times from Maskable Interrupt Request Generation to Interrupt Service
500
Interrupt Request Acknowledge Processing Algorithm
501
Interrupt Request Acknowledge Timing (Maximum Time)
502
Multiple Interrupt Servicing
503
Software Interrupt Request Acknowledge Operation
503
Interrupt Request Enabled for Multiple Interrupt During Interrupt Servicing
503
Multiple Interrupt Example
504
Interrupt Request Reserve
506
Interrupt Request Hold
506
Test Functions
507
Basic Configuration of Test Function
507
Flags Corresponding to Test Input Signals
507
Registers Controlling the Test Function
507
Test Input Factors
507
Format of Interrupt Mask Flag Register 1L
508
Test Input Signal Acknowledge Operation
509
Format of Interrupt Request Flag Register 1L
508
Key Return Mode Register Format
509
Chapter 22 External Device Expansion Function
511
External Device Expansion Functions
511
State of Ports 4 to 6 Pins in External Memory Expansion Mode
511
Pin Functions in External Memory Expansion Mode
511
Memory Map When Using External Device Expansion Function
512
External Device Expansion Function Control Register
516
Memory Expansion Mode Register Format
516
Memory Size Switching Register Format
517
Values When the Memory Size Switching Register Is Reset
517
External Device Expansion Function Timing
518
Instruction Fetch from External Memory
519
External Memory Read Timing
520
External Memory Write Timing
521
External Memory Read Modify Write Timing
522
Example of Connection with Memory
523
Connection Example of PD78054 and Memory
523
Chapter 23 Standby Function
525
Standby Function and Configuration
525
Standby Function
525
Standby Function Control Register
526
Oscillation Stabilization Time Select Register Format
526
Standby Function Operations
527
HALT Mode
527
HALT Mode Clear Upon Interrupt Request Generation
528
HALT Mode Release by RESET Input
529
Operation after HALT Mode Release
529
STOP Mode
530
STOP Mode Release by Interrupt Request Generation
531
Operation after STOP Mode Release
532
Release by STOP Mode RESET Input
532
Block Diagram of Reset Function
533
Chapter 24 Reset Function
533
Reset Function
533
Timing of Reset Input in STOP Mode by RESET Input
534
Timing of Reset Due to Watchdog Timer Overflow
534
Timing of Reset Input by RESET Input
534
Hardware Status after Reset
535
Chapter 25 Rom Correction
537
ROM Correction Functions
537
ROM Correction Configuration
537
Block Diagram of ROM Correction
537
Correction Address Registers 0 and 1 Format
538
ROM Correction Control Registers
539
Correction Control Register Format
539
ROM Correction Application
540
Connecting Example with EEPROM (Using 2-Wire Serial I/O Mode)
540
Storing Example to EEPROM (When One Place Is Corrected)
540
Initialization Routine
541
ROM Correction Operation
542
ROM Correction Example
543
Program Execution Flow
544
Program Transition Diagram (When One Place Is Corrected)
544
Program Transition Diagram (When Two Places Are Corrected)
545
Cautions on ROM Correction
546
Chapter 26 Pd78P054, 78P058
547
Pd78P054, 78P058
547
Differences between PD78P054, 78P058 and Mask ROM Versions
547
Differences between PD78P054 and 78P058
548
Examples of Memory Size Switching Register Settings ( PD78P054)
549
Memory Size Switching Register Format ( PD78P054)
549
Memory Size Switching Register ( PD78P054)
549
Examples of Memory Size Switching Register Settings ( PD78P058)
550
Memory Size Switching Register ( PD78P058)
550
Memory Size Switching Register Format ( PD78P058)
550
Internal Expansion RAM Size Switching Register
551
Value Set to the Internal Expansion RAM Size Switching Register
551
PROM Programming
552
Operating Modes
552
PROM Write Procedure
554
Page Program Mode Flowchart
554
Page Program Mode Timing
555
Byte Program Mode Flowchart
556
Byte Program Mode Timing
557
PROM Reading Procedure
558
PROM Read Timing
558
Erasure Procedure ( PD78P054KK-T and 78P058KK-T Only)
559
Opaque Film Masking the Window ( PD78P054KK-T and 78P058KK-T Only)
559
Screening of One-Time PROM Versions
559
Chapter 27 Instruction Set
561
Legends Used in Operation List
562
Operand Identifiers and Description Methods
562
Description of "Operation" Column
563
Description of "Flag Operation" Column
563
Operation List
564
Instructions Listed by Addressing Type
572
Appendix A Differences between Pd78054, 78054Y Subseries and Pd78058F, 78058Fy Subseries
577
A-1. Major Differences between PD78054, 78054Y Subseries and PD78058F, 78058FY Subseries
578
APPENDIX A DIFFERENCES between Μpd78054, 78054Y SUBSERIES and
579
Appendix B Development Tools
579
B-1. Development Tool Configuration
580
Language Processing Software
582
B.2.1 Hardware
584
B.2.2 Software
584
PROM Writing Tools
584
Hardware
584
Software
584
B.3 Debugging Tools
585
B.3.1 Hardware
585
Debugging Tools
585
Hardware
585
B.3.2 Software
587
Software
587
OS for IBM PC
589
Upgrading Former In-Circuit Emulators for 78K/0 Series to IE-78001-R-A
589
B-2. EV-9200GC-80 Drawing (for Reference Only)
590
B-3. EV-9200GC-80 Footprint (for Reference Only)
591
B-4. TGK-080SDW Drawing (for Reference) (Unit: MM)
592
Appendix C Embedded Software
593
Appendix D Register Index
595
Register Index
595
Appendix E Revision History
599
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