NEC PD78052 - Serial Interface Channel 0 Block Diagram

345
CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78054Y Subseries)
Figure 17-2. Serial Interface Channel 0 Block Diagram
Remark Output Control selects between CMOS output and N-ch open drain output.
CSIE0 COI WUP
CSIM
04
CSIM
03
CSIM
02
CSIM
01
CSIM
00
Serial Operating Mode Register 0
Control
Circuit
Output
Control
Selector
SI0/SB0/
SDA0/P25
PM25
Output
Control
SO0/SB1/
SDA1/P26
PM26
Output
Control
SCK0/
SCL/P27
PM27
Selector
P25
Output Latch
P26 Output Latch
CLD
P27
Output Latch
Internal Bus
BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT
Internal Bus
Stop Condition/
Start Condition/
Acknowledge
Detector
Serial Clock
Counter
Serial Clock
Control Circuit
CLR
D
SET
Q
Match
Acknowledge
Output Circuit
Interrupt
Request
Signal
Generator
ACKD
CMDD
RELD
WUP
Selector
Selector
TCL33TCL32TCL31TCL30
4
Timer Clock
Select
Register 3
f xx /2-f xx /2
8
INTCSI0
CLD SIC SVAM
BSYE
CLC WREL WAT1
WAT0
CSIM01
CSIM00
TO2
1/16
Divider
CSIM01
CSIM00
Interrupt Timing
Specify Register
Slave Address
Register (SVA)
SVAM
Serial Bus Interface
Control Register
2
Serial I/O Shift
Register 0 (SIO0)