NEC PD78052 - Page 25

25
LIST OF FIGURES (1/8)
Figure No. Title Page
3-1. Pin Input/Output Circuit of List....................................................................................................... 73
4-1. Pin Input/Output Circuit of List....................................................................................................... 89
5-1. Memory Map (
µ PD78052, 78052Y)............................................................................................... 91
5-2. Memory Map ( µ PD78053, 78053Y)............................................................................................... 92
5-3. Memory Map (
µ PD78054, 78054Y)............................................................................................... 93
5-4. Memory Map ( µ PD78P054)........................................................................................................... 94
5-5. Memory Map ( µ PD78055, 78055Y)............................................................................................... 95
5-6. Memory Map (
µ PD78056, 78056Y)............................................................................................... 96
5-7. Memory Map ( µ PD78058, 78058Y)............................................................................................... 97
5-8. Memory Map ( µ PD78P058, µ PD78P058Y)................................................................................... 98
5-9. Data Memory Addressing (
µ PD78052, 78052Y) ........................................................................... 101
5-10. Data Memory Addressing ( µ PD78053, 78053Y) ........................................................................... 102
5-11. Data Memory Addressing ( µ PD78054, 78054Y) ........................................................................... 103
5-12. Data Memory Addressing (
µ PD78P054) ....................................................................................... 104
5-13. Data Memory Addressing ( µ PD78055, 78055Y) ........................................................................... 105
5-14. Data Memory Addressing ( µ PD78056, 78056Y) ........................................................................... 106
5-15. Data Memory Addressing (
µ PD78058, 78058Y) ........................................................................... 107
5-16. Data Memory Addressing ( µ PD78P058, 78P058Y) ...................................................................... 108
5-17. Program Counter Configuration .................................................................................................... 109
5-18. Program Status Word Configuration ............................................................................................. 109
5-19. Stack Pointer Configuration........................................................................................................... 111
5-20. Data to be Saved to Stack Memory............................................................................................... 111
5-21. Data to be Reset from Stack Memory ........................................................................................... 111
5-22. General Register Configuration ..................................................................................................... 113
6-1. Port Types ..................................................................................................................................... 129
6-2. P00 and P07 Block Diagram ......................................................................................................... 135
6-3. P01 to P06 Block Diagram ............................................................................................................ 135
6-4. P10 to P17 Block Diagram ............................................................................................................ 136
6-5. P20, P21, P23 to P26 Block Diagram ........................................................................................... 137
6-6. P22 and P27 Block Diagram ......................................................................................................... 138
6-7. P20, P21, P23 to P26 Block Diagram ........................................................................................... 139
6-8. P22 and P27 Block Diagram ......................................................................................................... 140
6-9. P30 to P37 Block Diagram ............................................................................................................ 141
6-10. P40 to P47 Block Diagram ............................................................................................................ 142
6-11. Block Diagram of Falling Edge Detection Circuit........................................................................... 142
6-12. P50 to P57 Block Diagram ............................................................................................................ 143
6-13. P60 to P63 Block Diagram ............................................................................................................ 145
6-14. P64 to P67 Block Diagram ............................................................................................................ 145
6-15. P70 Block Diagram........................................................................................................................ 146
6-16. P71 and P72 Block Diagram ......................................................................................................... 147
6-17. P120 to P127 Block Diagram ........................................................................................................ 148